Target memory hierarchy specification in a multi-core computer processing system

1. A system for implementing prefetch instructions, the system comprising:

a first core processor;

a dedicated local cache corresponding to the first core processor; and

a second core processor including instructions for executing a prefetch instruction, the executing comprising:

sending, by the second core processor, an instruction to the dedicated local cache corresponding to the first core processor that directs the dedicated local cache corresponding to the first core processor to prefetch data for the first core processor from a memory location;

sending, by the dedicated local cache corresponding to the first core processor, a load request for data from the memory location responsive to receiving the instruction from the second core processor;

receiving, by the dedicated local cache corresponding to the first core processor, the data corresponding to the load request;

storing, on the dedicated local cache corresponding to the first core processor, the received data corresponding to the load request;

wherein the executing further comprises: sending, by the second core processor, a command to a system bus;

sending, by the system bus, the command to the first core processor and a main memory;

receiving, by the second core processor, a first response to the command from the first core processor that indicates that the first core processor requires access to the data that is specified in the command; and

receiving, by the second core processor, a second response to the command from the main memory that indicates that the main memory is capable of fulfilling the command,

wherein the sending, by the second core processor, of the instruction to the dedicated local cache corresponding to the first core processor is based on receiving the first and second responses.

2. The system of claim 1 , further comprising a system bus in communication with the first core processor and the second core processor, wherein the received data is received at the system bus and the storing of the received data on the dedicated local cache corresponding to the first core processor comprises transmitting the data from the system bus to the dedicated local cache corresponding to the first core processor.

3. The system of claim 1 , further comprising a system bus in communication with the first core processor and the second core processor, wherein the memory location is in a main memory, the received data is received at the system bus and the storing of the received data on the dedicated local cache corresponding to the first core processor comprises transmitting the data from the system bus to the dedicated local cache corresponding to the first core processor.

4. The system of claim 1 , wherein the memory location is in a main memory.

5. The system of claim 1 , wherein the memory location is in a second dedicated local cache corresponding to the second core processor.

6. The system of claim 1 , wherein the method further comprises:

re-issuing the instruction from the second core processor in response to determining that the dedicated local cache corresponding to the first core processor is unavailable to receive the retrieved data.

7. A computer implemented method for implementing prefetch instructions, the method comprising:

sending an instruction from a second core of a computer processor to a dedicated local cache corresponding to a first core of the computer processor that directs the dedicated local cache corresponding to the first core to prefetch data for the first core from a memory location;

sending, by the dedicated local cache corresponding to the first core, a load request for data from the memory location responsive to receiving the instruction from the second core;

receiving, by the dedicated local cache corresponding to the first core, the data corresponding to the load request;

storing, on the dedicated local cache corresponding to the first core, the received data corresponding to the load request;

wherein the sending the instruction further comprises:

sending, by the second core, a command to a system bus;

sending, by the system bus, the command to the first core and a main memory;

receiving, by the second core, a first response to the command from the first core that indicates that the first core requires access to the data that is specified in the command; and

receiving, by the second core, a second response to the command from the main memory that indicates that the main memory is capable of fulfilling the command,

wherein the sending, by the second core, of the instruction to the dedicated local cache corresponding to the first core is based on receiving the first and second responses.

8. The computer implemented method of claim 7 , wherein the storing of the received data comprises:

receiving the data at a system bus that is in communication with the computer processor, the system bus accessible to the computer processor via the second core and the first core; and

transmitting the data from the system bus to the dedicated local cache corresponding to the first core.

9. The computer implemented method of claim 7 , wherein the memory location is in a main memory.

10. The computer implemented method of claim 7 , wherein the memory location corresponds to the second core.

11. The computer implemented method of claim 7 , further comprising:

re-issuing the instruction from the second core upon determining that the first core is unavailable to receive the data.

12. A computer program product for implementing prefetch instructions, the computer program product comprising a non-transitory computer-readable storage medium having instructions embodied thereon, which upon execution of the instructions by a computer processor, the computer processor implements a method, the method comprising:

sending an instruction from a second core of a computer processor to a dedicated local cache corresponding to a first core of the computer processor that directs the dedicated local cache corresponding to the first core to prefetch data for the first core from a memory location;

sending, by the dedicated local cache corresponding to the first core, a load request for data from the memory location responsive to receiving the instruction from the second core;

receiving, by the dedicated local cache corresponding to the first core, the data corresponding to the load request;

storing, on the dedicated local cache corresponding to the first core, the received data corresponding to the load request;

wherein the sending the instruction further comprises:

sending, by the second core, a command to a system bus;

sending, by the system bus, the command to the first core and a main memory;

receiving, by the second core, a first response to the command from the first core that indicates that the first core requires access to the data that is specified in the command; and

receiving, by the second core, a second response to the command from the main memory that indicates that the main memory is capable of fulfilling the command,

wherein the sending, by the second core, of the instruction to the dedicated local cache corresponding to the first core is based on receiving the first and second responses.

13. The computer program product of claim 12 , wherein the storing of the received data comprises:

receiving the data at a system bus that is in communication with the computer processor, the system bus accessible to the computer processor via the second core and the first core; and

transmitting the data from the system bus to the dedicated local cache corresponding to the first core.

14. The computer program product of claim 12 , wherein the memory location is in a main memory.

15. The computer program product of claim 12 , wherein the memory location corresponds to the second core.

16. The computer program product of claim 12 , wherein the method further comprises:

re-issuing the instruction from the second core upon determining that the first core is unavailable to receive the data.