IP Library Granted Patent US 8,502,359
Granted Patent B2
US 8,502,359 · App. 13/141,222 · Granted Aug 6, 2013

Semiconductor device

Inventors: Akihiro Koga (Kyoto, JP); Taro Nishioka (Kyoto, JP)
Assignee: Rohm Co., Ltd.
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Quick Facts
Patent No.
US 8,502,359
App. No.
13/141,222
Granted
Aug 6, 2013
Kind
B2
Abstract

The semiconductor device according to the present invention includes a semiconductor chip, an island having an upper surface to which the semiconductor chip is bonded, a lead arranged around the island, a bonding wire extended between the surface of the semiconductor chip and the upper surface of the lead, and a resin package collectively sealing the semiconductor chip, the island, the lead and the bonding wire, while the lower surface of the island and the lower surface of the lead are exposed on the rear surface of the resin package, and the lead is provided with a recess concaved from the lower surface side and opened on a side surface thereof.

Claims (88)

1. A semiconductor device comprising:

a semiconductor chip;

an island having an upper surface to which the semiconductor chip is bonded;

a lead arranged around the island;

a bonding wire extending between the surface of the semiconductor chip and the upper surface of the lead; and

a resin package collectively sealing the semiconductor chip, the island, the lead and the bonding wire;

wherein the lower surface of the island and the lower surface of the lead are exposed on the rear surface of the resin package;

wherein the lead is provided with a recess concaved from the lower surface side and opened on a side surface thereof;

wherein the island is quadrangularly shaped in bottom plan view; and

wherein the lead is arranged on a portion opposed to each of four sides of the island in bottom plan view, and provided in a shape having a side parallel to the opposed side.

2. The semiconductor device according to claim 1 , wherein the recess has a portion arcuately shaped in bottom plan view.

3. The semiconductor device according to claim 1 , wherein the recess is opened on a side surface of the lead opposed to the island.

4. The semiconductor device according to claim 1 , wherein the area of the recess in bottom plan view is not more than half the total area of the lower surface of the lead.

5. The semiconductor device according to claim 1 , wherein

the lead has a side surface exposed on a side surface of the resin package, and

a portion of the lead along the exposed side surface is provided with a recessed groove concaved from the lower surface side of the lead over the total width in a direction along the side surface.

6. The semiconductor device according to claim 1 , wherein the lead further has a side parallel to a side of the resin package.

7. The semiconductor device according to claim 1 , wherein the lead has a side that is not parallel to the opposed side.

8. A semiconductor device comprising:

a semiconductor chip;

an island having an upper surface to which the semiconductor chip is bonded;

a lead arranged separated from the island;

a bonding wire extending between the surface of the semiconductor chip and the upper surface of the lead; and

a resin package collectively sealing the semiconductor chip, the island, the lead and the bonding wire, wherein

the lead is arranged in the vicinity of a corner portion of the resin package,

the island is inclined with respect to each side of the resin package,

a corner portion of the semiconductor chip being opposed to a central portion of each side of the resin package,

the lower surface of the island and the lower surface of the lead are exposed on the rear surface of the resin package, and

the lead is provided with a recess concaved from the lower surface side and opened on a side surface thereof.

9. The semiconductor device according to claim 8 , wherein the recess has a portion arcuately shaped in bottom plan view.

10. The semiconductor device according to claim 8 , wherein the recess is opened on a side surface of the lead opposed to the island.

11. The semiconductor device according to claim 8 , wherein

the island is quadrangularly shaped in bottom plan view, and

the lead is arranged on a portion opposed to each of four sides of the island in bottom plan view, and provided in a shape having a side parallel to the opposed side.

12. The semiconductor device according to claim 8 , wherein the area of the recess in bottom plan view is not more than half the total area of the lower surface of the lead.

13. The semiconductor device according to claim 8 , wherein

the lead has a side surface exposed on a side surface of the resin package, and

a portion of the lead along the exposed side surface is provided with a recessed groove concaved from the lower surface side of the lead over the total width in a direction along the side surface.

14. The semiconductor device according to claim 8 , wherein one side of the lower surface of the island is shorter than half a side of the resin package.

15. The semiconductor device according to claim 8 , wherein the recess includes a plurality of recesses formed on a plurality of sides forming the lead.

16. The semiconductor device according to claim 8 , wherein the island has a recess having a shape different from that of the recess of the lead.

17. The semiconductor device according to claim 8 , wherein the island has a groovelike recess extending along a diagonal line thereof.

18. The semiconductor device according to claim 8 , wherein

the island is quadrangularly shaped in bottom plan view, and

the lead is arranged on a portion opposed to each of four sides of the island in bottom plan view, and provided in a shape having a side parallel to the opposed side and a side not parallel to the opposed side.

19. A semiconductor device comprising:

a semiconductor chip;

an island having an upper surface to which the semiconductor chip is bonded;

a lead arranged around the island;

a bonding wire extending between the surface of the semiconductor chip and the upper surface of the lead; and

a resin package collectively sealing the semiconductor chip, the island, the lead and the bonding wire;

wherein the lower surface of the island and the lower surface of the lead are exposed on the rear surface of the resin package;

wherein the lead is provided with a recess concaved from the lower surface side and opened on a side surface thereof; and

wherein the recess has a portion arcuately shaped in bottom plan view.

20. The semiconductor device according to claim 19 , wherein the recess is opened on a side surface of the lead opposed to the island.

21. The semiconductor device according to claim 19 , wherein

the island is quadrangularly shaped in bottom plan view, and

the lead is arranged on a portion opposed to each of four sides of the island in bottom plan view, and provided in a shape having a side parallel to the opposed side.

22. The semiconductor device according to claim 19 , wherein the area of the recess in bottom plan view is not more than half the total area of the lower surface of the lead.

23. The semiconductor device according to claim 19 , wherein

the lead has a side surface exposed on a side surface of the resin package, and

a portion of the lead along the exposed side surface is provided with a recessed groove concaved from the lower surface side of the lead over the total width in a direction along the side surface.

24. The semiconductor device according to claim 21 , wherein the lead further has a side parallel to a side of the resin package.

25. The semiconductor device according to claim 19 , wherein

the island is quadrangularly shaped in bottom plan view, and

the lead is arranged on a portion opposed to each of four sides of the island in bottom plan view, and provided in a shape having a side parallel to the opposed side and a side not parallel to the opposed side.

26. A semiconductor device comprising:

a semiconductor chip;

an island having an upper surface to which the semiconductor chip is bonded, the island having a plurality of sides;

a lead arranged around the island;

a bonding wire extending between the surface of the semiconductor chip and the upper surface of the lead; and

a resin package being quadrangularly shaped in bottom plan view, the resin package collectively sealing the semiconductor chip, the island, the lead and the bonding wire, wherein

the lower surface of the island and the lower surface of the lead are exposed on the rear surface of the resin package,

the lead is provided with a recess concaved from the lower surface side and opened on a side surface thereof, and

the lead is provided on each corner of resin package in bottom plan view, and provided in a shape having sides opposed to sides of the island.

27. The semiconductor device according to claim 26 , wherein the recess has a portion arcuately shaped in bottom plan view.

28. The semiconductor device according to claim 26 , wherein the recess is opened on a side surface of the lead opposed to the island.

29. The semiconductor device according to claim 26 , wherein

the island is quadrangularly shaped in bottom plan view, and

the lead is arranged on a portion opposed to each of four sides of the island in bottom plan view, and provided in a shape having a side parallel to the opposed side.

30. The semiconductor device according to claim 26 , wherein the area of the recess in bottom plan view is not more than half the total area of the lower surface of the lead.

31. The semiconductor device according to claim 26 , wherein

the lead has a side surface exposed on a side surface of the resin package, and

a portion of the lead along the exposed side surface is provided with a recessed groove concaved from the lower surface side of the lead over the total width in a direction along the side surface.

32. The semiconductor device according to claim 29 , wherein the lead further has a side parallel to a side of the resin package.

33. The semiconductor device according to claim 26 , wherein

the island is quadrangularly shaped in bottom plan view, and

the lead is arranged on a portion opposed to each of four sides of the island in bottom plan view, and provided in a shape having a side parallel to the opposed side and a side not parallel to the opposed side.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 1, 2011
From: KOGA, AKIHIRO; NISHIOKA, TARO
To: ROHM CO., LTD.
Reel/Frame 026842/0912 →
Priority Claims (1)
JP 2008-326113 · Dec 22, 2008 · national
Continuity (1)
Related Publication 20120018896A1 · Jan 26, 2012