Semiconductor memory column decoder device and method
View Patent ↗Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in series and connected to a respective bit line. The memory devices also include a column decoder, a data register buffer unit, a row decoder, an erase control unit, and an input/output buffer unit. In one or more embodiments, the erase control unit applies voltages to the well to erase the memory cells in a manner that avoids breaking down p-n junctions formed by transistors fabricated in the well. In another embodiment, high voltage transistors are used to selectively isolate the bit lines from and couple the bit lines to a peripheral circuit in pairs so that each high voltage transistor is shared by two bit lines.
1. A memory device, comprising:
a plurality of serially-coupled memory cells fabricated in a well, each of the plurality of serially-coupled memory cells including a respective memory cell transistor;
a bit line coupled to the plurality of serially-coupled memory cells;
an additional transistor in the well, the additional transistor coupled between the bit line and one of the memory cell transistors, the additional transistor having a breakdown voltage;
an erase control unit configured to apply an erase voltage to the well; and
a bit line control unit coupled to the bit line and configured to bias the bit line to a non-zero voltage less than the erase voltage, the difference in potentials between the non-zero voltage and the erase voltage being less than the breakdown voltage of the additional transistor.
2. The memory device of claim 1 , wherein the additional transistor is configured to couple the memory cells to a data register.
3. The memory device of claim 2 , wherein the additional transistor is a column decoder transistor.
4. The memory device of claim 1 , further comprising:
a high voltage transistor coupled between the additional transistor and the data register, the high voltage transistor electrically isolated from the well.
5. The memory device of claim 1 , wherein the erase control unit is further configured to decouple the erase voltage from the well.
6. The memory device of claim 1 , wherein the additional transistor is capacitively coupled to the well.
7. The memory device of claim 1 , wherein the memory device is a NAND flash memory device.
8. A method comprising:
charging a well coupled to a bit line such that a voltage of the well is an erase voltage;
partially discharging the voltage of the well;
clamping a voltage of the bit line such that the difference between the voltage of the bit line and the voltage of the well is less than a breakdown voltage of a p-n junction in the well; and
further discharging the voltage of the well.
9. The method of claim 8 , wherein the voltage of the bit line is clamped at a non-zero voltage.
10. The method claim 8 , wherein said partially discharging comprises applying a discharge voltage to the bit line.
11. The method claim 8 , further comprising:
pre-charging the bit line, before said charging the well, such that the voltage of the bit line is equal to a supply voltage.
12. The method claim 8 , wherein said charging the well also charges the bit line such that the bit line voltage is the erase voltage minus a forward bias voltage.
13. The method claim 8 , wherein said further discharging occurs after said clamping.
14. The method of claim 13 , wherein said claiming occurs after said partially discharging.
15. A method of erasing memory cells in a memory array, the method comprising:
charging a well such that a voltage of the well is a first voltage, wherein the well comprises a plurality of memory cells fabricated therein;
initiating a discharge of the voltage of the well;
biasing a bit line coupled to the plurality of memory cells such that a difference between a voltage of the bit line and the voltage of the well is less than a breakdown voltage of a transistor in the well, wherein the transistor is coupled between the bit line and one of the plurality of memory cells; and
further discharging the voltage of the well.
16. The method of claim 15 , wherein the voltage of the bit line is biased to a non-zero voltage during discharge of the voltage of the well.
17. The method claim 15 , wherein the voltage of the well is discharged to zero volts.
18. The method claim 15 , wherein the transistor is a column decode transistor.
19. The method claim 18 , wherein the plurality of memory cells comprise memory cell transistors and the column decode transistor has identical operating characteristics as the memory cell transistors.
20. The method claim 18 , wherein the column decode transistor is configured to decrease the voltage of the bit line through a direct discharge path.
21. The method claim 15 , wherein the voltage of the bit line is less than the first voltage.
22. The method claim 15 , wherein the memory cells comprise n-channel field effect transistors and the well is a p-type well.
23. The method claim 15 , wherein the plurality of memory cells comprise a plurality of floating gates, and wherein said charging the well causes a plurality of electrons on the plurality of floating gates of the plurality of memory cells to tunnel into the well.