Write circuitry for hierarchical memory architectures
A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.
1. A global input and output circuitry comprising:
a global clock generation circuitry to generate a global write clock signal; and
a global write circuitry coupled to the global clock generation circuitry, wherein the global write circuitry is configured to transfer a write-data, the global write circuitry comprising:
a full transmission gate to facilitate transfer of the write-data based on the global write clock signal;
a plurality of global sub-write circuitries, each global sub-write circuitry comprising:
a storage element coupled to the full transmission gate, wherein the storage element stores the write-data; and
a decoupling circuit configured to disable the full transmission gate based on the write-data stored in the storage element.
2. The global input and output circuitry as claimed in claim 1 , wherein the decoupling circuit receives inputs from a global write true data bus and a global write false data bus to disable the full transmission gate.
3. The global input and output circuitry as claimed in claim 1 , wherein each of the global sub-write circuitry comprises an odd-delay circuit to reset the storage element.
4. The global input and output circuitry as claimed in claim 3 , wherein the odd-delay circuit is programmable.
5. The global input and output circuitry as claimed in claim 1 , wherein each of the global sub-write circuitry comprises a pre-charging circuit.
6. The global input and output circuitry as claimed in claim 5 , wherein the pre-charging circuit is programmable.
7. The global input and output circuitry as claimed in claim 1 , wherein the full transmission gate is configured to select the global sub-write circuitry for writing the write-data.
8. The global input and output circuitry as claimed in claim 1 , wherein the storage element comprises a reset-set latch.