IP Library Granted Patent US 8,527,698
Granted Patent B2
US 8,527,698 · App. 12/963,048 · Granted Sep 3, 2013

Parity-based raid system configured to protect against data corruption caused by the occurrence of write holes

Inventor: Luca Bert (Cumming, GA)
Assignee: LSI Corporation
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Quick Facts
Patent No.
US 8,527,698
App. No.
12/963,048
Granted
Sep 3, 2013
Kind
B2
Abstract

A RAID system is provided in which the RAID controller of the system causes a predetermined number, N, of IO commands to be queued in a memory element, where N is a positive integer. After the N IO commands have been queued, the RAID controller writes N locks associated with the N IO commands in parallel to a service memory device. The RAID controller then writes N stripes of data and parity bits associated with the N IO commands to the PDs of the system to perform striping and parity distribution. If a catastrophic event, such as a power failure, occurs, the RAID controller reads the locks from the service memory device and causes parity to be reconstructed for the stripes associated with the locks. These features improve write performance while preventing the occurrence of data corruption caused by write holes.

Claims (35)

1. A parity-based Redundant Array of Inexpensive Disks (RAID) system comprising:

a RAID controller comprising:

a processor; and

a local memory device;

a plurality of physical disks (PDs) in communication with the RAID controller;

a nonvolatile service memory device in communication with the RAID controller; and

wherein at least a portion of the local memory device is allocated for use as a queue for queuing N input/output (IO) commands received from a computer that is external to the RAID system, where N is a positive integer, and wherein the processor generates a lock associated with each received IO command and causes the received IO commands and the locks to be queued in the local memory device, and wherein the processor determines when N IO commands have been queued in the local memory device, and wherein when N IO commands have been queued, the processor causes the N respective locks associated with the N respective queued IO commands to be written to N respective lock storage locations of the service memory device, and wherein after the N respective locks have been written to the nonvolatile service memory device, the processor causes N respective stripes of data and parity bits associated with the N respective IO commands to be written to the PDs.

2. The parity-based RAID system of claim 1 , wherein the nonvolatile service memory device comprises a circular buffer.

3. The parity-based RAID system of claim 2 , wherein the circular buffer has M lock storage locations capable of storing M locks, where M is a positive integer that is equal to or greater than N.

4. The parity-based RAID system of claim 3 , wherein M is greater than N.

5. The parity-based RAID system of claim 1 , wherein the parity-based RAID system implements RAID level 5.

6. The parity-based RAID system of claim 1 , wherein the local memory device is a volatile memory device.

7. The parity-based RAID system of claim 1 , wherein if an electrical power failure occurs in the RAID system, then after electrical power is restored to the RAID system, the RAID controller reads the locks from the nonvolatile service memory device and reconstructs parity bits for each IO command associated with the locks read by the RAID controller from the nonvolatile service memory device.

8. A method for use in a parity-based Redundant Array of Inexpensive Disks (RAID) system for protecting against a potential for data corruption caused by an occurrence of a write hole, the method comprising:

receiving input/output (IO) commands in a RAID controller of the RAID system from a computer that is external to the RAID system;

in a processor of the RAID controller, generating a respective lock for each respective IO command received in the RAID controller;

in a local memory device of the RAID controller, queuing N of the received IO commands and N of the locks associated with the N IO commands, where N is a positive integer;

in the processor of the RAID controller, determining when N IO commands have been queued in the local memory device, and, when N IO commands have been queued, causing the N locks associated with the N queued IO commands to be written to N respective lock storage locations of a service memory device of the RAID system; and

in the processor of the RAID controller, after the N respective locks have been written to the service memory device, causing N respective stripes of data and parity bits associated with the N respective IO commands to be written to physical devices (PDs) of the RAID system.

9. The method of claim 8 , wherein the service memory device is a circular buffer.

10. The method of claim 9 , wherein the circular buffer has M lock storage locations capable of storing M locks, where M is a positive integer that is equal to or greater than N.

11. The method of claim 10 , wherein M is greater than N.

12. The method of claim 8 , wherein the RAID system implements RAID level 5.

13. The method of claim 8 , wherein the local memory device is a volatile memory device.

14. The method of claim 8 , further comprising:

in the processor of the RAID controller, if an electrical power failure occurs in the RAID system, when electrical power is restored to the RAID system, performing a reboot process to reboot the processor; and

in the processor, after the processor reboots, performing a reconstruction process that reads the locks that are stored in the service memory device from the service memory device and reconstructs parity bits for each IO command associated with the locks read from the service memory device.

15. A non-transitory computer-readable medium (CRM) having a computer program embodied thereon for use in a parity-based Redundant Array of Inexpensive Disks (RAID) system for protecting against a potential for data corruption caused by a potential occurrence of a write hole, the non-transitory CRM comprising:

a first set of computer instructions for receiving input/output (IO) commands in a RAID controller of the RAID system from a computer that is external to the RAID system;

a second set of computer instructions for generating a respective lock for each respective IO command received in the RAID controller;

a third set of computer instructions for queuing N of the received IO commands and N of the locks associated with the N IO commands in a local memory device of the RAID controller, where N is a positive integer;

a fourth set of instructions for determining when N IO commands have been queued in the local memory device, and, when N IO commands have been queued in the local memory device, for causing the N locks associated with the N queued IO commands to be written to N lock storage locations of a service memory device of the parity-based RAID system; and

a fifth set of instructions for causing N respective stripes of data and parity bits associated with the N respective IO commands to be written to physical devices (PDs) of the RAID system after the N respective locks have been written to the N lock storage locations of the service memory device.

16. The non-transitory CRM of claim 15 , further comprising:

a sixth set of instructions for performing a reconstruction process after an electrical power has occurred and electrical power has been restored to the RAID system, the sixth set of instructions reading the locks that are stored in the service memory device from the service memory device and reconstructing parity bits for each IO command associated with the locks read from the service memory device.

Assignments (10)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER IN THE INCORRECT US PATENT NO. 8,876,094 PREVIOUSLY RECORDED ON REEL 047351 FRAME 0384. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 049248/0558 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF THE MERGER PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0910. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047351/0384 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0910 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2011
From: BERT, LUCA
To: LSI CORPORATION
Reel/Frame 025772/0770 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2010
From: GRIFFITHS, MICHAEL; BICKLEY, DANIEL JAMES
To: ROLLS-ROYCE GOODRICH ENGINE CONTROL SYSTEMS LIMITED
Reel/Frame 025468/0500 →
Continuity (2)
Provisional Application 61357176 · Jun 22, 2010
Related Publication 20110314218A1 · Dec 22, 2011