System and method of error correction of control data at a memory device

1. A method comprising:

in a memory device including an error correction coding (ECC) engine and multiple storage elements including a group of storage elements, wherein the memory device is configured to store information to the storage elements according to a page format, the page format including a data portion and a parity portion, performing:

initiating a compression operation to compress data to be stored in the group of storage elements;

selecting one of a first mode of the ECC engine to generate a first number of parity bits and a second mode of the ECC engine to generate a second number of parity bits, the selected mode based on an extent of compression of the compressed data;

encoding the compressed data to generate parity bits corresponding to the compressed data; and

adding additional data to the compressed data to increase a storage size of a formatted word;

storing the formatted word including the compressed data and the parity bits to the group of storage elements according to the page format, wherein the compressed data is stored in the data portion and at least some of the parity bits are stored in the parity portion.

2. The method of claim 1 , wherein the first number of parity bits corresponds to a size of the parity portion and wherein the second number of parity bits is greater than the size of the parity portion.

3. The method of claim 2 , wherein when the second mode is selected a first portion of the parity bits is stored in the parity portion and a second portion of the parity bits is stored in the data portion.

4. The method of claim 3 , wherein the second mode is selected in response to the data portion having sufficient space to include the compressed data and the second portion of the parity bits.

5. The method of claim 1 , wherein the compressed data is encoded using the ECC engine in the selected mode.

6. The method of claim 1 , wherein the memory device includes a controller and wherein the data includes control data generated at the controller.

7. The method of claim 6 , wherein the control data comprises data of a type selected from the group consisting of logical and physical block address tables for the storage elements; indices, pointers, and offsets for data structures at the memory device; and wear leveling data for the memory device.

8. A method comprising:

in a memory device including an error correction coding (ECC) engine and multiple storage elements, wherein the memory device is configured to store information at the storage elements according to a page format, the page format including a data portion and a parity portion, performing:

reading a page of data including compressed data and parity bits from the storage elements according to the page format wherein the page of data includes additional data added to the compressed data to increase a storage size of a formatted word, wherein the compressed data is included in the data portion of the page and at least some of the parity bits are included in the parity portion of the page;

decoding the compressed data at the ECC engine using the parity bits; and

decompressing the compressed data to generate decompressed data,

wherein the ECC engine is configurable to operate according to a first mode when all of the parity bits are included in the parity portion of the page or to operate according to a second mode when a first portion of the parity bits is included in the parity portion of the page and a second portion of the parity bits is included in the data portion of the page.

9. The method of claim 8 , wherein the memory device includes a controller and wherein the decompressed data includes control data generated at the controller.

10. The method of claim 9 , wherein the control data comprises data of a type selected from the group consisting of logical and physical block address tables for the storage elements; indices, pointers, and offsets for data structures at the memory device; and wear leveling data for the memory device.

11. A data storage device comprising:

a memory including multiple storage elements; and

a controller coupled to the memory and configured to store information to the storage elements according to a page format, the page format including a data portion and a parity portion, wherein the controller comprises:

an error correction coding (ECC) engine; and

a compression module coupled to the ECC engine and configured to receive and compress data provided to the ECC engine for encoding,

wherein the ECC engine is configurable to operate in a first mode to generate a first number of parity bits or to operate in a second mode to generate a second number of parity bits based on an extent of compression of the data, and

wherein the controller is configured to store a page including the compressed data and parity bits to the storage elements according to the page format, wherein the compressed data is stored in the data portion of the page and at least some of the parity bits are stored in the parity portion of the page, and wherein the controller is configured to add additional data to the compressed data to increase a storage size of a formatted word.

12. The data storage device of claim 11 , wherein the ECC engine further comprises:

error detection coding circuitry configured to encode compressed data; and

error correction coding circuitry configured to decode the encoded compressed data.

13. The data storage device of claim 11 , wherein the first number of parity bits corresponds to a size of the parity portion of the page and wherein the second number of parity bits is greater than the size of the parity portion of the page.

14. The data storage device of claim 13 , wherein when the ECC engine operates in the second mode a first portion of the parity bits is stored in the parity portion and a second portion of the parity bits is stored in the data portion.

15. The data storage device of claim 14 , wherein the second mode is selected in response to the data portion having sufficient size to include the compressed data and the second portion of the parity bits.

16. The data storage device of claim 11 , wherein the controller is further configured to generate control data and wherein the received data includes the control data.

17. The data storage device of claim 16 , wherein the control data comprises data of a type selected from the group consisting of logical and physical block address tables for the memory; indices, pointers, and offsets for data structures at the memory; and wear leveling data for the data storage device.

18. The data storage device of claim 11 , wherein the memory includes a flash memory.

19. A data storage device comprising:

a memory including multiple storage elements; and

a controller coupled to the memory and configured to read information from the storage elements according to a page format, the page format including a data portion and a parity portion, wherein the controller comprises:

an error correction coding (ECC) engine; and

a decompression module coupled to the ECC engine and configured to receive and decompress decoded data provided by the ECC engine,

wherein the ECC engine is operative to decode a page of compressed data and parity bits read from the memory according to the page format, wherein the compressed data is included in the data portion of the page and at least some of the parity bits are included in the parity portion of the page, and wherein the controller is configured to add additional data to the compressed data to increase a storage size of a formatted word, and

wherein the ECC engine is configured to operate according to a first mode when all of the parity bits are included in the parity portion of the page or to operate according to a second mode when a first portion of the parity bits is included in the parity portion of the page and a second portion of the parity bits is included in the data portion of the page.

20. The data storage device of claim 19 , wherein the decompressed decoded data includes control data usable by the controller.

21. The data storage device of claim 19 , wherein the memory includes a flash memory.