Semiconductor structure and method for manufacturing the same
The present invention provides a method for manufacturing a semiconductor structure, comprising the steps of: depositing an interlayer dielectric layer ( 105 ) on a semiconductor substrate ( 101 ) to cover a source/drain region ( 102 ) and a gate stack on the semiconductor substrate ( 101 ); etching the interlayer dielectric layer and the source/drain region, so as to form a contact hole ( 110 ) extending into the source/drain region; conformally forming an amorphous layer ( 111 ) on an exposed part of the source/drain region; forming a metal silicide layer ( 113 ) on a surface of the amorphous layer ( 111 ); and filling the contact hole ( 110 ) with a contact metal ( 114 ). Correspondingly, the present invention further provides a semiconductor structure. The present invention etches the source/drain region so that the exposed part comprises the bottom and a sidewall, thereby expanding the contact area between the contact metal in the contact hole and the source/drain region, and reducing the contact resistance. The present invention effectively eliminates EOR defects caused by the amorphous ion implantation by forming an amorphous substance by a selective deposition.
1. A method for manufacturing a semiconductor structure, comprising:
depositing an interlayer dielectric layer ( 105 ) on a semiconductor substrate ( 101 ) to cover a source/drain region ( 102 ) and a gate stack on the semiconductor substrate ( 101 );
etching the interlayer dielectric layer ( 105 ) and the source/drain region ( 102 ), so as to expose a part of the source/drain region ( 102 ) and form a contact hole ( 110 ) extending into the source/drain region ( 102 );
conformally forming an amorphous layer ( 111 ) on the exposed part of the source/drain region ( 102 );
forming a metal silicide layer ( 113 ) on a surface of the amorphous layer ( 111 ); and
filling the contact hole ( 110 ) with a contact metal ( 114 ).
2. The method according to claim 1 , wherein
the amorphous layer ( 111 ) is conformally formed by a selective deposition process or an epitaxial growth process.
3. The method according to claim 1 , wherein
the amorphous layer ( 111 ) has a thickness larger than a portion thereof used for forming the metal silicide layer.
4. The method according to claim 1 , wherein the amorphous layer is one of amorphous silicon, amorphous SiGe and amorphous SiC.
5. The method according to claim 1 , wherein after conformally forming the amorphous layer ( 111 ), the method further comprises implanting doping ions into the amorphous layer ( 111 ).
6. The method according to claim 1 , wherein the exposed part of the source/drain region ( 102 ) comprises the bottom of the contact hole ( 110 ) and a part of the sidewall extending from the bottom.
7. The method according to claim 1 , wherein the source/drain region ( 102 ) is a raised source/drain region.
8. The method according to claim 1 , wherein the contact metal ( 114 ) is made of one of W, TiAl alloy and Al, or combinations thereof.
9. The method according to claim 1 , wherein
the source/drain region ( 102 ) comprises an etching stop layer made of a material different from that of other portions in the source/drain region.
10. The method according to claim 9 , wherein
the etching stop layer is flushed with the bottom of the gate stack.
11. The method according to claim 9 , wherein
the etching stop layer is made of silicon; and
a portion in the source/drain region above the etching stop layer is made of SiGe.