Flash memory and method for forming the same

1. A method for forming a flash memory cell, comprising:

providing a substrate;

successively forming a first dielectric layer, a first polysilicon layer, a second dielectric layer, a second polysilicon layer and a hard mask layer on the substrate;

successively etching the hard mask layer, the second polysilicon layer, the second dielectric layer, the first polysilicon layer and the first dielectric layer to form an opening to expose a portion of the substrate;

successively forming a third dielectric layer and a third polysilicon layer over the hard mask layer and the opening's sidewalls and bottom surface;

etching the third polysilicon layer and the third dielectric layer to expose the hard mask layer and a portion of the substrate, the remaining third polysilicon layer and the remaining third dielectric layer forming a word line and a word line dielectric layer on each of the opening's sidewalls;

implanting ions into the exposed portion of the substrate to form a source region;

forming a source line on the surface of the source region of the exposed semiconductor substrate, and an isolating dielectric layer between the source line and each word line;

removing the hard mask layer;

forming a first spacer on a side of each word line dielectric layer away from the word line; and

successively etching the second polysilicon layer, the second dielectric layer, the first polysilicon layer and the first dielectric layer with the first spacers as a mask until the substrate is exposed, to form a gate stack comprising a control gate, a control gate dielectric layer, a floating gate and a floating gate dielectric layer on each side of the source line.

2. The method according to claim 1 , wherein forming the source line comprises:

forming a spacer over the word line dielectric layer's sidewall and part of the word line's sidewall, wherein the spacer acts as an isolating dielectric layer between the word line and the source line to be formed;

filling the opening up with polysilicon until the polysilicon covers the word lines and the hard mask layer;

chemical mechanical polishing the polysilicon until the hard mask layer is exposed; and

etching back the polysilicon in the opening to expose the word line and part of the isolating dielectric layer.

3. The method according to claim 1 , wherein the source line's top surface is lower than the isolating dielectric layer's top surface.

4. The method according to claim 1 , further comprising forming isolating structures in the semiconductor substrate, which extends into the first dielectric layer and further into the first polysilicon layer.

5. The method according to claim 1 , wherein the first dielectric layer, the second dielectric layer and the third dielectric layer comprise silicon dioxide.

6. The method according to claim 1 , wherein the hard mask layer comprises silicon nitride.

7. The method according to claim 1 , wherein the hard mask layer comprises a thickness ranging from about 2000 Å to about 4000 Å.

8. The method according to claim 1 , wherein the first spacer comprises silicon dioxide.

9. The method according to claim 1 , wherein the third dielectric layer is formed by a high temperature CVD process.

10. The method according to claim 1 , further comprising forming a second spacer on a sidewall of the gate stack on a side of the gate stack away from the source line, after the gate stack is formed.

11. The method according to claim 10 , wherein the second spacer comprises silicon nitride.

12. The method according to claim 1 , further comprises forming a drain region in the substrate on a side of each gate stack away from the source line after the gate stack is formed.