Tightly coupled scalar and boolean processor with result vector subunit controlled by instruction flow
Methods and apparatus relating to a tightly coupled scalar and Boolean processor are described. In an embodiment, a Boolean unit may include a result vector subunit. The result vector subunit may be controlled by an instruction flow that is managed by a scalar unit. Other embodiments are also disclosed.
1. An apparatus comprising:
a scalar unit;
a Boolean unit, the Boolean unit comprising a result vector subunit to store comparison result data in a result vector having a plurality of bits, wherein each bit in the result vector corresponds to a comparison operation or a Boolean operation on pairs of bits, wherein the result vector subunit is controlled by an instruction flow managed by the scalar unit;
a communication facility to couple the scalar and Boolean units; and
a condition code unit to capture a cumulative status of a plurality of operations,
wherein a policy engine is to classify packets based on the comparison result data,
wherein the policy engine is to perform bulk comparisons for a threshold number of cycles through suppression of interpretation of subsequent information during the threshold number of cycles.
2. The apparatus of claim 1 , wherein the Boolean unit comprises an ALU subunit.
3. The apparatus of claim 2 , wherein the ALU subunit comprises a plurality of one bit wide subunits, wherein each one bit wide subunit performs a Boolean operation on selected bits from the result vector unit.
4. The apparatus of claim 3 , wherein at least one of the one bit wide subunits receives an input from a different one of the one bit wide subunits.
5. The apparatus of claim 2 , wherein the ALU subunit is about one bit wide.
6. The apparatus of claim 2 , wherein the ALU subunit is controlled by an instruction flow managed by the scalar unit.
7. The apparatus of claim 2 , wherein the ALU subunit comprises a gang operations unit, wherein the gang operations unit performs a Boolean operation on a packed word of data in a single clock cycle.
8. The apparatus of claim 1 , wherein the communication facility is to provide a communication channel from the scalar unit to the Boolean unit to communicate one or more single-bit results that are transferred into the result vector subunit in response to performance of an operation by the scalar unit.
9. The apparatus of claim 8 , wherein the single-bit result comprises a condition code.
10. The apparatus of claim 1 , further comprising a sequencer to fetch one or more microwords corresponding to one or more units or to execute the instruction flow.
11. The apparatus of claim 10 , wherein the one or more units comprise one or more of: the scalar unit, the Boolean unit, the communication facility, the condition code unit, or an interface to an external memory.
12. The apparatus of claim 1 , wherein the scalar unit comprises a mask and rotate subunit.
13. The apparatus of claim 12 , wherein the mask and rotate subunit comprises a split adder.
14. The apparatus of claim 1 , further comprising an arithmetic logic unit (ALU) coupled to the scalar and Boolean units.
15. The apparatus of claim 14 , wherein the scalar unit comprises the ALU.
16. The apparatus of claim 1 , wherein the result vector subunit is about one bit wide.
17. The apparatus of claim 1 , wherein the condition code unit is to assist in one or more operations comprising: capturing a status of a single operation and capturing a status of a plurality of operations.
18. The apparatus of claim 1 , further comprising logic to perform one or more operations on one or more bits within the result vector subunit, wherein the one or more operations comprise setting each bit individually or clearing each bit individually.
19. The apparatus of claim 1 , wherein at least a portion of a packed word of the result vector subunit is selected as a scalar operand for an operation to be performed by the scalar unit.
20. The apparatus of claim 1 , wherein the result vector subunit is accessible as at least one packed word of bits.
21. The apparatus of claim 1 , wherein the result vector subunit is implemented as a register file, wherein the register file is accessible as individual bits.
22. The apparatus of claim 1 , wherein the result vector subunit is to store the comparison result data in pairs of odd and even bits.
23. The apparatus of claim 1 , wherein a first portion of the subsequent information is to be compared by a first comparator during a first cycle of the threshold number of cycles and a second portion of the subsequent information is to be compared by a second comparator during the first cycle of the threshold number of cycles.