Method of measuring delay in an integrated circuit

1. A method of measuring signal delay in an integrated circuit comprising:

applying a clock signal at a first register input and a second register input,

applying a test signal to an input of the first register, wherein an output signal S from the first register is input to a circuit under test, and wherein an output signal D from the circuit under test is input into the second register, based on an output signal from the second register and the output signal D, detecting whether the output signal S and output signal D occur in a common part of the clock signal.

2. A method as claimed in claim 1 further comprising varying a clock signal frequency of the clock signal until the output signal S and output signal D do not fall in a common part of the clock signal.

3. A method as claimed in claim 2 comprising varying the frequency by incrementally increasing the frequency.

4. A method as claimed in claim 2 comprising, setting a minimum clock frequency and maximum clock frequency, setting the actual clock frequency between said minimum clock frequency and maximum clock frequency, if the output signal S and output signal D fall in the common part of the clock signal, setting the actual frequency as the new minimum frequency, if the output signal S and output signal D do not fall in a common part of the clock signal, setting the actual frequency as the maximum frequency and repeating the steps.

5. A method as claimed in claim 2 , further comprising:

making multiple repetition of the steps at various clock signal frequencies; and

constructing a cumulative distribution of the number of times the output signal S and the output signal D do not occur in a common part of the clock signal at the various clock signal frequencies.

6. A method as claimed in claim 5 , wherein constructing the cumulative distribution is based on only one of rising or falling transitions in the output signal S and the output signal D.

7. A method as claimed in claim 6 , further comprising deriving a measure of delay based on the clock signal frequency for which the probability of the cumulative distribution is 0.5.

8. A method as claimed in claim 5 , wherein constructing the cumulative distribution is based on both of rising and falling transitions in the output signal S and the output signal D.

9. A method as claimed in claim 8 , further comprising deriving a measure of delay based on the clock signal frequency for which the probability of the cumulative distribution is 0.25.

10. A method as claimed in claim 1 further comprising deriving a signal delay value dependent on the clock frequency.

11. A method as claimed in claim 1 in which the common part of the clock signal corresponds to an interval during which the clock signal occupies the same state, or to a full clock period.

12. A method as claimed in claim 1 in which the step of detecting whether the output signal S and output signal D fall in the common part of the clock signal is determined taking into account latencies in the circuit.

13. A method as claimed in claim 1 in which the output signal S and output signal D comprise at least of one corresponding rising or falling signal transitions.

14. A method as claimed in claim 1 in which the common clock signal is generated within the integrated circuit.

15. A method as claimed in claim 1 further comprising storing values of clock frequency and corresponding occurrences of the output signal S and output signal D falling or not falling within a common part of the clock signal.

16. A method as claimed in claim 15 in which the values are stored as a count and the count is incremented using a flip flop component.

17. A method as claimed in claim 15 in which the values are stored for only one of corresponding rising or falling transitions in the output signal S and output signal D.

18. A method as claimed in claim 15 in which the values are stored for both of corresponding rising and falling transitions in the output signal S and output signal D.

19. A method as claimed in claim 15 further comprising identifying a clock signal frequency occurring in a transition region between regions where all output signals S and output signals D fall in a common part of the clock signal and where all output signals S and output signals D do not fall in a common part of the clock signal, and deriving a measure of delay from said clock signal frequency.

20. A method as claimed in claim 19 in which the transition region is selected to correspond to a worst case internal latency value.

21. A method as claimed in claim 1 further comprising attributing a delay to each of multiple signal paths, mapping the signal paths and providing a path delay map for the integrated circuit.

22. A method as claimed in claim 21 further comprising assigning integrated circuit functions according to the path delay map.

23. A method as claimed in claim 22 further comprising remeasuring signal delays after a predetermined period of operation of the integrated circuit and remapping functions dependent on any changes in the path delay map.

24. A method as claimed in claim 1 in which the integrated circuit comprises a programmable logic integrated circuit.

25. A method of designing an integrated circuit comprising measuring delay according to a method as claimed in claim 1 , providing a path delay map and assigning integrated circuit function according to the path delay map.

26. An apparatus for measuring signal delay in an integrated circuit comprising

a first register;

a second register;

a clock signal generator configured to apply a common clock signal at a first register input and a second register input, wherein an output signal S from the first register is configured to be applied as input to a circuit under test, and wherein an output signal D from the circuit under test is configured to be applied as input into the second register, a test signal generator configured to apply a test signal to an input of the first register, and a detector configured to detect whether the output signal S applied at the input and an output signal D detected at the output fall in the common part of the clock signal.