Systems and methods for variable level use of a multi-level flash memory
Various embodiments of the present invention provide systems, methods and circuits for use of a memory system. As one example, an electronics system is disclosed that includes a memory bank, a memory access controller circuit, and an encoding circuit. The memory bank includes a plurality of multi-bit memory cells that each is operable to hold at least two bits. The memory access controller circuit is operable to determine a use frequency of a data set maintained in the memory bank. The encoding circuit is operable to encode the data set to yield an encoded output for writing to the memory bank. The encoding level for the data set is selected based at least in part on the use frequency of the data set.
1. An electronic system, the system comprising:
a memory bank including a plurality of multi-bit memory cells, wherein each of the plurality of multi-bit memory cells is operable to hold at least two bits;
a memory access controller circuit, wherein the memory access controller circuit is operable to determine a use frequency of a data set maintained in the memory bank; and
an encoding circuit, wherein the encoding circuit is operable to encode the data set to yield an encoded output for writing to the memory bank, wherein an encoding level is operable to control a number of bits to be stored in the multi-bit memory cells, and wherein the encoding level for is selected based at least in part on the use frequency of the data set.
2. The electronic system of claim 1 , wherein the electronic system further comprises:
a decoding circuit, wherein the decoding circuit is operable to reverse the encoding applied by the encoding circuit.
3. The electronic system of claim 1 , wherein the data set includes at least two bits, wherein the encoding level includes at least a high use level and a low use level, and wherein the encoded output is selected from a group consisting of: a single two bit output representing the two data bits, and a series of two two bit outputs representing the two data bits.
4. The electronic system of claim 3 , wherein the encoded output is selected to be the single two bit output representing the two data bits when the use frequency is lower than a threshold corresponding to the low use level.
5. The electronic system of claim 4 , wherein selection of the single two bit output representing the two data bits results in a tradeoff of increased bit density for decreased lifecycle.
6. The electronic system of claim 3 , wherein the encoded output is selected to be the series of two two bit outputs representing the two data bits when the use frequency is higher than a threshold corresponding to the high use level.
7. The electronic system of claim 6 , wherein selection of the series of two two bit outputs representing the two data bits results in a tradeoff of decreased bit density for increased lifecycle.
8. The electronic system of claim 1 , wherein each of the plurality of multi-bit memory cells is operable to hold at least three bits, and wherein the data set includes at least three data bits, and wherein the encoding circuit is operable to encode the three data bits as the encoded output to the plurality of multi-bit memory cells, and wherein the encoded output is selected from a group consisting of: a single three bit output representing the three data bits, and a series of three three bit outputs representing the three data bits.
9. The electronics system of claim 1 , wherein determining the use frequency of a data set includes determining the frequency of writes of the data set to the memory bank.
10. The electronics system of claim 9 , wherein determining the use frequency of a data set further includes determining the frequency of reads of the data set from the memory bank.
11. The electronics system of claim 1 , wherein the plurality of multi-bit memory cells is a plurality of multi-bit flash memory cells.
12. The electronics system of claim 1 , wherein the plurality of multi-bit memory cells is part of a flash memory system communicably coupled to a processor.
13. The electronics system of claim 12 , wherein the processor is further communicably coupled to:
an I/O device, and
a random access memory.
14. A method for varying the lifecycle of a memory cell based upon use frequency, the method comprising:
providing a memory device, wherein the memory device includes a plurality of multi-bit memory cells, and wherein each of the plurality of multi-bit memory cells is operable to hold at least two bits;
receiving a data set, wherein the data set includes at least two data bits;
determining a use frequency of the data set;
selectably encoding the two data bits as two two bit outputs when the use frequency indicates a high use level; and
writing the two two bit outputs to two of the plurality of multi-bit memory cells when the use frequency indicates the high use level.
15. The method of claim 14 , wherein the method further comprises:
selectably encoding the two data bits as a single two bit output when the use frequency indicates a low use level; and
writing the single two bit output to one of the plurality of multi-bit memory cells when the use frequency indicates the low use level.
16. The method of claim 14 , wherein the selectably encoding is governed at least in part by comparing the use frequency with a threshold level, wherein the high use level is indicated when the use frequency exceeds the threshold level, and wherein the low use level is indicated when the use frequency is less than the threshold level.
17. The method of claim 14 , wherein determining the use frequency of the data set includes determining the frequency of writes of the data set to the memory bank.
18. The method of claim 17 , wherein determining the use frequency of the data set further includes determining the frequency of reads of the data set from the memory bank.
19. A memory circuit, the memory circuit comprising:
a flash memory device, wherein the flash memory device includes a plurality of multi-bit memory cells, and wherein each of the plurality of multi-bit memory cells is operable to hold at least two bits;
a memory access controller circuit, wherein the memory access controller circuit is operable to determine a use frequency of a data set maintained in the flash memory device; and
an encoding circuit, wherein the encoding circuit is operable to encode the data set to yield an encoded output for writing to the flash memory device, wherein an encoding level is operable to control a number of bits to be stored in the multi-bit memory cells, and wherein the encoding level set is selected based at least in part on the use frequency of the data set.
20. The memory circuit of claim 19 , wherein the memory circuit further comprises:
a decoding circuit, wherein the decoding circuit is operable to reverse the encoding applied by the encoding circuit.
21. A system, the system comprising:
a memory bank including a plurality of multi-bit memory cells, wherein each of the plurality of multi-bit memory cells is chargeable to distinguishable voltage levels, wherein each of the distinguishable voltage levels corresponds to at least two bits;
a memory access controller circuit, wherein the memory access controller circuit is operable to determine a use frequency of a data set maintained in the memory bank; and
an encoding circuit, wherein the encoding circuit is operable to encode the data set to yield an encoded output for writing to the memory bank, wherein an encoding level is operable to control a number of bits to be stored in the multi-bit memory cells, and wherein the encoding level is selected based at least in part on the use frequency of the data set.
22. The system of claim 21 , wherein the encoding level is selected from a group consisting of: an encoding level using a first subset of the distinguishable voltage levels to yield a first number of bits per cell, and an encoding level using a second subset of the distinguishable voltage levels to yield a second number of bits per multi-bit memory cell; wherein the second number of bits per cell is more than the first number of bits per multi-bit memory cell.
23. The system of claim 21 , wherein the electronic system further comprises:
a decoding circuit, wherein the decoding circuit is operable to reverse the encoding applied by the encoding circuit.
24. The system of claim 21 , wherein the data set includes at least two bits, wherein the encoding level includes at least a high use level and a low use level, and wherein the encoded output is selected from a group consisting of: a single two bit output representing the two data bits, and a series of two two bit outputs representing the two data bits.
25. The system of claim 24 , wherein the encoded output is selected to be the single two bit output representing the two data bits when the use frequency is lower than a threshold corresponding to the low use level.
26. The system of claim 25 , wherein selection of the single two bit output representing the two data bits results in a tradeoff of increased bit density for decreased lifecycle.
27. The system of claim 24 , wherein the encoded output is selected to be the series of two two bit outputs representing the two data bits when the use frequency is higher than a threshold corresponding to the high use level.
28. The system of claim 27 , wherein selection of the series of two two bit outputs representing the two data bits results in a tradeoff of decreased bit density for increased lifecycle.
29. The system of claim 21 , wherein each of the plurality of multi-bit memory cells is operable to hold at least three bits, and wherein the data set includes at least three data bits, and wherein the encoding circuit is operable to encode the three data bits as the encoded output to the plurality of multi-bit memory cells, and wherein the encoded output is selected from a group consisting of: a single three bit output representing the three data bits, and a series of three three bit outputs representing the three data bits.
30. The system of claim 21 , wherein determining the use frequency of a data set includes determining the frequency of writes of the data set to the memory bank.
31. The system of claim 30 , wherein determining the use frequency of a data set further includes determining the frequency of reads of the data set from the memory bank.