Safe memory storage by internal operation verification
The disclosed invention provides a structure and method for detecting address line (e.g., wordline, bitline) memory failures. In one embodiment, the method and structure comprise generating an address signature, by re-encoding an internally generated address signal from activated elements (e.g., wordlines) inside a memory array. The regenerated address signature may be compared with a requested memory address location. If the regenerated address signature and memory location are equal than there is no error in the memory array, but if the regenerated address signature and memory location are equal than an error is present in the memory array. Accordingly, re-encoding an address signature provides a closed loop check that a wordline and/or bitline, that was actually activated in a memory array, was the correct requested wordline and/or bitline, that no other wordlines or bitlines were also triggered, and that the wordline and/or bitline is continuous.
1. A memory block, comprising:
a host processing unit configured to provide a memory operation request comprising a requested memory address;
a first memory array having a plurality of address lines;
a first address decoder configured to receive the requested memory address and to selectively activate a respective address line associated with the requested memory address; and
an address signature generator configured to receive the memory operation request and further configured to generate an address signature based upon the activated address line and to compare the generated address signature and the requested memory address,
wherein an error signal is generated if the address lines of the generated address signature are not the same as the address lines of the requested memory address.
2. The memory block of claim 1 , wherein the address signature generator comprises:
a second memory array configured to store additional address information; and
an address comparator configured to receive the generated address signature and the requested memory address, compare the generated address signature and the requested memory address, and to generate the error signal.
3. The memory block of claim 2 , wherein the second memory array comprises a read only memory (ROM) and wherein the additional address information comprises the address signature.
4. The memory block of claim 1 , wherein the address signature generator comprises:
a second address decoder configured to receive the memory operation request and to generate wordline activation signals indicating the wordlines that are to be generated based upon the received memory operation request; and
a logic circuitry coupled to the first memory array and the second address decoder,
wherein the logic circuit is configured to receive wordline activation signals from the first memory array and the generated wordline activation signals from the second address decoder and to determine erroneously activated wordlines therefrom.
5. The memory block of claim 4 , wherein the logic gate comprises an exclusive OR gate.
6. The memory block of claim 1 , wherein:
the first memory array comprises a plurality of substantially parallel wordlines driven by a row decoder coupled to a first end of the plurality of wordlines, and
the address signature generator is coupled to a second opposite end of the plurality of wordlines than the row decoder.
7. The memory block of claim 6 , wherein:
the first memory array comprises a plurality of substantially parallel bitlines, substantially perpendicular to the plurality of wordlines, read by a sense amplifier coupled to a first end of the plurality of bitlines, and
a second address signature generator is coupled to a second opposite end of the plurality of bitlines than the sense amplifier.
8. The memory block of claim 1 , wherein the address signature comprises an uncompressed address or a lossless encoding of the generated address.
9. The memory block of claim 1 , wherein upon generation of an error signal, the host processing unit is given bus wire control to retry writing data to the first memory array.
10. The memory block of claim 1 , further comprising a test circuit configured to selectively generate an erroneous address signature that may be provided to the address comparator, thereby intentionally causing the address comparator to output the error signal.
11. A method for detecting errors in a data stream being transmitted in a computer system, comprising:
providing a requested address location within a first memory array for a memory operation request to an address decoder coupled to the first memory array and an address signature generator;
selectively activating one or more address lines in the first memory array based upon the requested address location;
generating a regenerated address signature based upon the selectively activated address lines; and
comparing the requested address location to the regenerated address signature, wherein the comparison identifies the presence of address line errors in the first memory array.
12. The method of claim 11 , wherein the address signature comprises an uncompressed address or a lossless encoding of the regenerated address.
13. The method of claim 11 , wherein generating a regenerated address signature comprises:
storing a plurality of data bits having additional address information in a second memory array, wherein respective data bits comprise address information corresponding to the address signature of a wordline; and
selectively outputting the stored additional address information based upon activation of the wordline.
14. The method of claim 13 , wherein the second memory array comprises a read only memory (ROM).
15. The method of claim 11 , wherein:
the first memory array comprises a plurality of substantially parallel wordlines driven by a row decoder coupled to a first end of the plurality of wordlines, and
a first address signature generator is coupled to a second opposite end of the plurality of wordlines than the row decoder.
16. The method of claim 15 , wherein:
the first memory array comprises a plurality of substantially parallel bitlines, substantially perpendicular to the plurality of wordlines, read by a sense amplifier coupled to a first end of the plurality of bitlines, and
a second address signature generator is coupled to a second opposite end of the plurality of bitlines than the sense amplifier.
17. The method of claim 11 , further comprising:
selectively generating an erroneous address signature that may be provided for comparison to the requested address location instead of the generated address signature,
wherein the erroneous address signature may be utilized to test operation of the comparison.
18. The method of claim 11 , further comprising retrying writing data to the first memory array upon identification of the address line errors in the first memory array.
19. A memory block, comprising:
a re-encoding mechanism coupled to a plurality of substantially parallel address lines, comprised within an electronic storage array having a matrix structure, and configured to re-generate an address signature based upon one or more of the plurality of address lines which are actually activated during an electronic storage operation; and
a comparison circuit configured to compare the re-generated address signature and a requested memory address.
20. The memory block of claim 19 ,
wherein if the address lines of the re-generated address signature are the same as address lines of the requested memory address, then no address line error is present, and
wherein if the address lines of the re-generated address signature are not the same as address lines of the requested memory address, then an address line error is present.
21. The memory block of claim 19 ,
wherein if address lines of the re-generated address signature are equivalent to address lines of the requested memory address, then no address line error is present, and
wherein if address lines of the re-generated address signature are not equivalent to address lines of the requested memory address, then an address line error is present.