IP Library Granted Patent US 8,569,731
Granted Patent B2
US 8,569,731 · App. 12/726,743 · Granted Oct 29, 2013

Nonvolatile memory device and method for manufacturing same

Inventors: Takuya Konno (Kanagawa-ken, JP); Hiroyuki Fukumizu (Mie-ken, JP); Kazuhito Nishitani (Kanagawa-ken, JP)
Assignee: Kabushiki Kaisha Toshiba
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,569,731
App. No.
12/726,743
Granted
Oct 29, 2013
Kind
B2
Abstract

A nonvolatile memory device includes: at least one first interconnection extending in a first direction; at least one second interconnection disposed above the first interconnection and extending in a second direction nonparallel to the first direction; a memory cell disposed between the first interconnection and the second interconnection at an intersection of the first interconnection and the second interconnection and including a memory element; and an element isolation layer disposed between the memory cells. At least one dielectric film with a higher density than the element isolation layer is disposed on a sidewall surface of the memory cell.

Claims (10)

1. A nonvolatile memory device comprising:

at least one first interconnection extending in a first direction;

at least one second interconnection disposed above the first interconnection and extending in a second direction nonparallel to the first direction;

a memory cell disposed between the first interconnection and the second interconnection at an intersection of the first interconnection and the second interconnection and including a memory element;

an element isolation layer disposed between the memory cells; and

at least one dielectric film with a higher density than the element isolation layer being disposed on a sidewall surface of the memory cell,

the element isolation layer including a low-k material, a dielectric constant of the element isolation layer being lower than a dielectric constant of the dielectric film, a sidewall surface and a bottom surface of the element isolation layer being covered with the continuous dielectric film.

2. The device according to claim 1 , wherein a concentration of impurities contained in the element isolation layer is higher than a concentration of impurities contained in the dielectric film.

3. The device according to claim 1 , wherein the dielectric film includes a first dielectric film and a second dielectric film, the first dielectric film with a higher density than the element isolation layer is disposed on the sidewall surface of the memory cell, and the second dielectric film with a lower dielectric constant than the first dielectric film and with a higher density than the element isolation layer is disposed on the first dielectric film.

4. The device according to claim 1 , wherein a rectifying element is provided in the memory cell.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 26, 2010
From: KONNO, TAKUYA; FUKUMIZU, HIROYUKI; NISHITANI, KAZUHITO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 024288/0752 →
Priority Claims (1)
JP 2009-075275 · Mar 25, 2009 · national
Continuity (1)
Related Publication 20100244114A1 · Sep 30, 2010