Three-dimensional semiconductor memory devices
Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess is provided, which extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells are provided on the substrate. This vertical stack of nonvolatile memory cells includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers are provided, which extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.
1. A nonvolatile memory device, comprising:
a substrate having a well region of second conductivity type therein and a common source region of first conductivity type on the well region, said common source region forming a P-N rectifying junction with the well region;
a recess in said substrate, said recess extending entirely through the common source region and at least partially into the well region; and
a vertical stack of nonvolatile memory cells on said substrate, said vertical stack of nonvolatile memory cells comprising:
a vertical stack of spaced-apart gate electrodes on said substrate;
a vertical active region on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess; and
gate dielectric layers extending between respective ones of the vertical stack of spaced-apart gate electrodes and said vertical active region;
wherein at least one of a sidewall and bottom of said recess defines an interface between said vertical active region and the well region at a point in said substrate extending below the P-N rectifying junction between the common source region and the well region.
2. The memory device of claim 1 , wherein each of said gate dielectric layers comprises a composite of a tunnel insulating layer in contact with said vertical active region, a charge storage layer on the tunnel insulating layer, a barrier dielectric layer on the charge storage layer and a blocking insulating layer extending between the barrier dielectric layer and a respective gate electrode; and wherein the barrier dielectric layer comprises a material having a greater bandgap relative to the blocking insulating layer.
3. The memory device of claim 1 , wherein said recess has a protective dielectric layer on a sidewall thereof; and wherein the protective dielectric layer extends between said vertical active region and the common source region.
4. The memory device of claim 3 , wherein a bottom of said recess defines an interface between said vertical active region and the well region.
5. The memory device of claim 1 , wherein said vertical active region has a cylindrical shape.
6. The memory device of claim 5 , wherein said vertical active region comprises a plurality of concentrically-arranged semiconductor layers of first conductivity type having equivalent or different dopant concentrations therein.
7. The memory device of claim 6 , wherein each of said gate dielectric layers comprises a composite of a tunnel insulating layer in contact with said vertical active region, a charge storage layer on the tunnel insulating layer, a barrier dielectric layer on the charge storage layer and a blocking insulating layer extending between the barrier dielectric layer and a respective gate electrode; and wherein the barrier dielectric layer comprises a material having a greater bandgap relative to the blocking insulating layer.
8. The memory device of claim 6 , wherein said vertical stack of spaced-apart gate electrodes has an opening extending therethrough that is aligned to said recess; wherein said gate dielectric layers have a cylindrical shape; and wherein said gate dielectric layers are concentrically-arranged relative to the plurality of concentrically-arranged semiconductor layers.
9. The memory device of claim 1 , wherein said vertical active region comprises an active region plug filling the recess and a cylindrically-shaped active layer on the active region plug.
10. The memory device of claim 9 , wherein the cylindrically-shaped active layer comprises a plurality of concentrically-arranged semiconductor layers of first conductivity type having equivalent or different doping concentrations therein.
11. The memory device of claim 9 , further comprising a vertical stack of at least two spaced-apart gate electrodes of ground selection transistors extending opposite the active region plug.
12. The memory device of claim 11 , wherein the ground selection transistors have respective gate dielectric layers on a side of the active region plug; and wherein the gate dielectric layers of said vertical stack of nonvolatile memory cells comprise different materials relative to the gate dielectric layers of the ground selection transistors.
13. The memory device of claim 9 , further comprising at least one gate electrode of a ground selection transistor extending opposite the active region plug.
14. The memory device of claim 13 , wherein the ground selection transistor has a gate dielectric layer on a sidewall of the active region plug; and wherein the gate dielectric layers of said vertical stack of nonvolatile memory cells comprise different materials relative to the gate dielectric layer of the ground selection transistor.