Magnetic memory and manufacturing method thereof
According to one embodiment, a manufacturing method of a magnetic memory includes forming a magnetoresistive element in a cell array section on a semiconductor substrate, forming a dummy element in a peripheral circuit section on the semiconductor substrate, the dummy element having the same stacked structure as the magnetoresistive element and being arranged at the same level as the magnetoresistive element, collectively flattening the magnetoresistive element and the dummy element, applying a laser beam to the dummy element to form the dummy element into a non-magnetic body, and forming an upper electrode on the flattened magnetoresistive element.
1. A manufacturing method of a magnetic memory, the method comprising:
forming a magnetoresistive element in a cell array section on a semiconductor substrate;
forming a dummy MTJ element in a peripheral circuit section on the semiconductor substrate, the dummy MTJ element having the same stacked structure as the magnetoresistive element and being arranged at the same level as the magnetoresistive element;
collectively flattening the magnetoresistive element and the dummy MTJ element;
applying a laser beam to the dummy MTJ element to form the dummy MTJ element into a non-magnetic body; and
forming an upper electrode on the flattened magnetoresistive element.
2. The method of claim 1 , further comprising forming a mask layer that covers the magnetoresistive element before the applying the laser beam.
3. The method of claim 2 , wherein the mask layer is made of a material having a high laser wavelength absorption factor.
4. The method of claim 2 , wherein the mask layer is made of a graphite-based material.
5. The method of claim 1 , wherein the magnetoresistive element comprises a reference layer having an invariable direction of magnetization, a recording layer having a variable direction of magnetization, and a non-magnetic layer provided between the reference layer and the recording layer.
6. The method of claim 1 , further comprising:
forming a lower electrode in the cell array section; and
forming an insulating layer around the lower electrode and in the peripheral circuit section,
wherein the magnetoresistive element is formed on the lower electrode, and
the dummy MTJ element is formed on the insulating layer.
7. The method of claim 1 , further comprising:
forming a select transistor electrically connected to the magnetoresistive element in the cell array section; and
forming a peripheral transistor in the peripheral circuit section.
8. A manufacturing method of a magnetic memory, the method comprising:
forming an magnetoresistive element in a cell array section on a semiconductor substrate;
forming a dummy MTJ element in a peripheral circuit section on the semiconductor substrate, the dummy MTJ element having the same stacked structure as the magnetoresistive element and being arranged at the same level as the magnetoresistive element;
collectively flattening the magnetoresistive element and the dummy MTJ element;
removing the dummy MTJ element; and
forming an upper electrode on the flattened magnetoresistive element.
9. The method of claim 8 , further comprising filling an opening formed by removing the dummy MTJ element with the same material as the upper electrode.
10. The method of claim 8 , further comprising forming a mask layer in the cell array section and the peripheral circuit section to cover the magnetoresistive element and expose the dummy MTJ element.
11. The method of claim 10 , wherein the removing the dummy MTJ element comprises etching the dummy MTJ element using the mask layer as a mask.
12. The method of claim 8 , wherein the magnetoresistive element comprises a reference layer having an invariable direction of magnetization, a recording layer having a variable direction of magnetization, and a non-magnetic layer provided between the reference layer and the recording layer.
13. The method of claim 8 , further comprising:
forming a lower electrode in the cell array section; and
forming an insulating layer around the lower electrode and in the peripheral circuit section,
wherein the magnetoresistive element is formed on the lower electrode, and
the dummy MTJ element is formed on the insulating layer.
14. The method of claim 8 , further comprising:
forming a select transistor electrically connected to the magnetoresistive element in the cell array section; and
forming a peripheral transistor in the peripheral circuit section.