IP Library Granted Patent US 8,575,686
Granted Patent B2
US 8,575,686 · App. 13/114,681 · Granted Nov 5, 2013

Nonvolatile semiconductor memory transistor, nonvolatile semiconductor memory, and method for manufacturing nonvolatile semiconductor memory

Inventors: Fujio Masuoka (Tokyo, JP); Hiroki Nakamura (Tokyo, JP)
Assignee: Unisantis Electronics Singapore Pte Ltd.
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Quick Facts
Patent No.
US 8,575,686
App. No.
13/114,681
Granted
Nov 5, 2013
Kind
B2
Abstract

A nonvolatile semiconductor memory transistor included in a nonvolatile semiconductor memory includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the substrate side, a hollow pillar-shaped floating gate arranged so as to surround the outer periphery of the channel region in such a manner that a tunnel insulating film is interposed between the floating gate and the channel region, and a hollow pillar-shaped control gate arranged so as to surround the outer periphery of the floating gate in such a manner that an inter-polysilicon insulating film is interposed between the control gate and the floating gate. The inter-polysilicon insulating film is arranged so as to be interposed between the floating gate and the upper, lower, and inner side surfaces of the control gate.

Claims (12)

1. A nonvolatile semiconductor memory transistor comprising:

an island-shaped semiconductor having a source region, a channel region, and a drain region in order from surface of a substrate;

a hollow pillar-shaped floating gate surrounding an outer periphery of the channel region and a tunnel insulating film between the floating gate and the channel region, the hollow pillar-shaped floating gate having a circumferential recess therein; and

a hollow pillar-shaped control gate surrounding an outer periphery of the floating gate and at least partially within the circumferential recess; and

an inter-polysilicon insulating film residing in the circumferential recess between the control gate and the floating gate,

wherein the inter-polysilicon insulating film resides between the floating gate and an upper surface, a lower surface, and a lateral side surface of the control gate,

wherein the control gate faces the floating gate in the recess and the lateral side surface of the control gate does not face the island-shaped semiconductor in a vertical direction, and

wherein the upper surface of the floating gate does not face the island-shaped semiconductor in the vertical direction.

2. The nonvolatile semiconductor memory transistor according to claim 1 , further comprising a first insulating film on the substrate below the floating gate, wherein the first insulating film has a thickness that is greater than a thickness of at least one of the tunnel oxide film and the inter-polysilicon insulating film.

3. A nonvolatile semiconductor memory comprising the nonvolatile semiconductor memory transistor according to claim 1 ,

wherein the nonvolatile semiconductor memory transistor includes a plurality of nonvolatile semiconductor memory transistors in a row direction among row and column directions of the substrate, and

wherein a drain region of at least one of the plurality of nonvolatile semiconductor memory transistors is electrically connected to a second source line in a column direction among the row and column directions of the substrate.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2011
From: UNISANTIS ELECTRONICS JAPAN LTD.
To: UNISANTIS ELECTRONICS SINGAPORE PTE LTD.
Reel/Frame 026970/0670 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 24, 2011
From: MASUOKA, FUJIO; NAKAMURA, HIROKI
To: UNISANTIS ELECTRONICS (JAPAN) LTD.
Reel/Frame 026334/0735 →
Priority Claims (1)
JP 2010-133057 · Jun 10, 2010 · national
Continuity (2)
Provisional Application 61353303 · Jun 10, 2010
Related Publication 20110303966A1 · Dec 15, 2011