Combined binary/decimal fixed-point multiplier and method
View Patent ↗A combined binary/decimal fixed-point multiplier that uses BCD-4221 recoding for the decimal digits. This allows the use of binary carry-save hardware to perform decimal addition with a small correction. The described designs provide an improved reduction tree organization to reduce the area and delay of the multiplier and improved reduction tree components that leverage the redundant decimal encodings to help reduce delay. A split reduction tree architecture is also introduced that reduces the delay of the binary product with only a small increase in total area. Area and delay estimates are presented that show that the proposed designs have significant area improvements over separate binary and decimal multipliers while still maintaining similar latencies for both decimal and binary operations.
1. A combined binary decimal multiplier comprising:
a plurality of binary multiple generators configured to receive a first input and to generate a first output based on the first input;
a plurality of binary recording elements configured to receive a second input and to generate a second output; based on the second input;
a partial product selector having an binary decimal doubling unit configured to receive the first output and the second output and to generate a third output;
a split 33:2 partial product reduction tree configured to receive the third output and to generate a binary output and a decimal output, the split 33:2 partial product reduction tree comprising a plurality of 3:2 carry save adders; and
a 128 bit combined binary/decimal conditional quaternary tree adder configured to perform carry-propagate addition of the binary output and the decimal output.
2. The combined binary decimal multiplier of claim 1 wherein the binary decimal doubling unit is configured to use BCD-4221 encoding for binary multiplication.
3. The combined binary decimal multiplier of claim 1 wherein, the binary decimal doubling unit receives data as a 4-bit value, said value representing a BCD-4221 digit or a 4-bit binary integer, and a selection signal indicates the type of data.
4. The combined binary decimal multiplier of claim 1 wherein the split 33:2 partial product reduction tree is configured to reduce latency of the binary output by sharing a top half of the split 33:2 partial product reduction tree.
5. The combined binary decimal multiplier of claim 1 wherein the split 33:2 partial product reduction tree does not include a 4:2 compressor.
6. A method for performing combined binary decimal multiplication comprising:
receiving a first input by a binary multiple generator;
generating a first output based on the first input by the binary multiple generator;
receiving a second input by a binary recording element;
generating a second output based on the second input by the binary recording element;
receiving the first output and the second output by a partial product selector;
generating a third output by the partial product selector based on the first output and he second output;
receiving the third output by a split 33:2 partial product reduction tree, the split 33:2 partial product reduction tree comprising a plurality of 3:2 carry save adders;
generating a binary output and a decimal output by the split 33:2 partial product reduction tree based on the third output; and
performing carry-propagate addition of the binary output and the decimal output by a 128 bit combined binary/decimal conditional quaternary tree adder.
7. The method for performing combined binary decimal multiplication of claim 6 wherein the binary decimal doubling unit is configured to use BCD-4221 encoding for binary multiplication.
8. The method for performing combined binary decimal multiplication of claim 6 wherein, the binary decimal doubling unit receives data as a 4-bit value, said value representing a BCD-4221 digit or a 4-bit binary integer, and a selection signal indicates the type of data.
9. The method for performing combined binary decimal multiplication of claim 6 wherein the split 33:2 partial product reduction tree is configured to reduce latency of the binary output by sharing a top half of the split 33:2 partial product reduction tree.
10. The method for performing combined binary decimal multiplication of claim 6 wherein the split 33:2 partial product reduction tree does not include a 4:2 compressor.