Semiconductor stacks including catalytic layers
A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode layer, forming a catalytic layer on the first electrode layer, optionally annealing the catalytic layer, forming a dielectric layer on the catalytic layer, optionally annealing the dielectric layer, forming a second electrode layer on the dielectric layer, and optionally annealing the capacitor stack. Advantageously, the electrode layers are TiN, the catalytic layer is MoO 2−x where x is between 0 and 2, and the physical thickness of the catalytic layer is between about 0.5 nm and about 10 nm, and the dielectric layer is ZrO 2 .
1. A semiconductor layer stack comprising:
a first electrode layer formed on a substrate;
a catalytic layer formed on the first electrode layer,
wherein the catalytic layer comprises one or more layers of unoxidized molybdenum interspersed with one or more layers of MoO 2 ;
a dielectric layer formed on the catalytic layer; and
a second electrode layer formed on the dielectric layer.
2. The semiconductor layer stack of claim 1 , wherein the first electrode layer comprises one of TiN, TaN, TiAlN, W, WN, Mo, or Mo 2 N.
3. The semiconductor layer stack of claim 2 , wherein the first electrode layer comprises TiN.
4. The semiconductor layer stack of claim 1 wherein the catalytic layer has a physical thickness between about 0.5 nm and about 10 nm.
5. The semiconductor layer stack of claim 1 , wherein the dielectric layer comprises one of SiO 2 , a bilayer of SiO 2 and Si x N y , SiON, Al 2 O 3 , HfO 2 , HfSiO x , ZrO 2 , Ta 2 O 5 , TiO 2 , SrTiO 3 (STO), SrBaTiO x (SBT), PbZrTiO x (PZT) or doped versions of the same.
6. The semiconductor layer stack of claim 5 , wherein the dielectric layer comprises one of ZrO 2 or TiO 2 .
7. The semiconductor layer stack of claim 1 , wherein the second electrode layer comprises one of TiN, TaN, TiAlN, W, WN, Mo, or Mo 2 N.
8. The semiconductor layer stack of claim 7 , wherein the second electrode layer comprises TiN.
9. The semiconductor layer stack of claim 1 , wherein the first electrode layer comprises TiN, wherein a physical thickness of the catalytic layer is between about 0.5 nm and about 10 nm, wherein the dielectric layer comprises ZrO 2 , and wherein the second electrode layer comprises TiN.
10. The semiconductor layer stack of claim 1 , wherein the dielectric layer comprises ZrO 2 .
11. The semiconductor layer stack of claim 1 , wherein the first electrode has a thickness of between about 5 nm and 50 nm.
12. The semiconductor layer stack of claim 1 , wherein the catalytic layer comprises no oxygen-rich phases.
13. The semiconductor layer stack of claim 1 , wherein the catalytic layer comprises a crystalline phase.
14. The semiconductor layer stack of claim 1 , wherein the dielectric layer further comprises a dopant.
15. The semiconductor layer stack of claim 14 , wherein the dopant is non-uniformly distributed throughout the dielectric layer.
16. The semiconductor layer stack of claim 1 , wherein the dielectric layer comprises a nanolaminate of different films.
17. The semiconductor layer stack of claim 1 , wherein the dielectric layer has a thickness of between about 6 nm and 10 nm.