Multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections
Some exemplary embodiments of a multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections have been disclosed. One exemplary embodiment comprises a PQFN semiconductor package comprising a leadframe, a driver integrated circuit (IC) coupled to the leadframe, a plurality of vertical conduction power devices coupled to the leadframe, and a plurality of wirebonds providing electrical interconnects, including at least one wirebond from a top surface electrode of one of the plurality of vertical conduction power devices to a portion of the leadframe, wherein the portion of the leadframe is electrically connected to a bottom surface electrode of another of the plurality of vertical conduction power devices. In this manner, efficient multi-chip circuit interconnections can be provided in a PQFN package using low cost leadframes.
1. A power quad flat no-lead (PQFN) semiconductor package comprising:
a leadframe comprising a plurality of die pads;
a driver integrated circuit (IC) coupled to a first die pad of the leadframe;
a plurality of vertical conduction power transistors including a first group of vertical conduction power transistors coupled to a common die pad of the leadframe separated from the first die pad, and a second group of vertical conduction power transistors individually coupled to separate die pads of the leadframe;
the common die pad and the separate die pacts being exposed at a bottom surface of the PQFN semiconductor package for increased thermal conductivity;
a top surface electrode of one of the first group of vertical conduction power transistors being electrically connected to a bottom surface electrode of one of the second group of vertical conduction power transistors;
at least one wirebond providing direct electrical connection between the driver IC and one of the plurality of vertical conduction power transistors.
2. The PQFN semiconductor package of claim 1 , wherein the PQFN semiconductor package is configured as a full bridge power device.
3. The PQFN semiconductor package of claim 1 , wherein the leadframe is selectively plated with silver for enhanced adhesion.
4. The PQFN semiconductor package of claim 1 , wherein the first group of vertical conduction power transistors is positioned near a first edge of the package, and wherein the second group of vertical conduction power transistors is positioned near a second edge of the package.
5. The PQFN semiconductor package of claim 1 , wherein the plurality of vertical conduction power transistors has six (6) vertical conduction power transistors, the first group of vertical conduction power transistors has three (3) vertical conduction power transistors and the second group of vertical conduction power transistors has three (3) vertical conduction power transistors.
6. The PQFN semiconductor package of claim 1 , wherein the plurality of vertical conduction power transistors comprises power MOSFETs.
7. The PQFN semiconductor package of claim 1 , wherein the plurality of vertical conduction power transistors comprises IGBTs.
8. The PQFN semiconductor package of claim 1 , wherein a thickness of the PQFN semiconductor package is 0.9 mm or less.
9. The PQFN semiconductor package of claim 1 , wherein a footprint of the PQFN semiconductor package is 12 mm by 12 mm or less.
10. A power quad flat no-lead (PQFN) semiconductor package comprising:
a leadframe;
a driver integrated circuit (IC) coupled to the leadframe;
a plurality of vertical conduction power transistors coupled to the leadframe, a top surface electrode of one of the plurality of vertical conduction power transistors being electrically connected to a portion of the leadframe, wherein the portion of the leadframe is electrically connected to a bottom surface electrode of another of the plurality of vertical conduction power transistors and wherein the portion of the leadframe is exposed at a bottom surface of the PQFN semiconductor package for increased thermal conductivity;
at least one wirebond providing direct electrical connection between the driver IC and a first of the plurality of vertical conduction power transistors;
wherein the plurality of vertical conduction power transistors is divided into a first group positioned on a single die pad near a first edge of the PQFN semiconductor package and a second group positioned on individual die pads near a second edge of the PQFN semiconductor package, the first group including the one of the plurality of vertical conduction power transistors and the second group including the another of the plurality of vertical conduction power transistors; wherein the driver integrated circuit is disposed on a die pad separated from the single die pad and the individual die pads.
11. The PQFN semiconductor package of claim 10 , wherein the PQFN semiconductor package is configured as a full bridge power device.
12. The PQFN semiconductor package of claim 10 , wherein the leadframe is selectively plated with silver for enhanced adhesion.
13. The PQFN semiconductor package of claim 10 , wherein the plurality of vertical conduction power transistors has six (6) vertical conduction power transistors.
14. The PQFN semiconductor package of claim 10 , wherein the plurality of vertical conduction power transistors comprises power MOSFETs.
15. The PQFN semiconductor package of claim 10 , wherein the plurality of vertical conduction power transistors comprises IGBTs.
16. The PQFN semiconductor package of claim 10 , wherein a thickness of the PQFN semiconductor package is 0.9 mm or less.
17. The PQFN semiconductor package of claim 10 , wherein a footprint of the PQFN semiconductor package is 12 mm by 12 mm or less.
18. The PQFN semiconductor package of claim 10 , wherein the leadframe comprises a copper (Cu) alloy.