Unpacking a variable number of data bits
Unpacking a variable number of data bits is provided. A structure includes an input port operable to receive one or more input data units including a plurality of packed bits of data, each of the one or more input data units including a header and a payload, the header including a predetermined number of bits and identifying a format of the payload and a length of the payload, and the payload including a variable number of bits. The structure further includes a circuit operable to identify and unpack the one or more input data units based on the header and the payload of each of the one or more input data units. The structure further includes an output port operable to transmit one or more output data units including the unpacked one or more input data units, once per clock cycle.
1. A structure comprising:
an input port operable to receive one or more input data units comprising a plurality of packed bits of data, each of the one or more input data units comprising a header and a payload, the header comprising a predetermined number of bits and identifying a format of the payload and a length of the payload, and the payload comprising a variable number of bits;
a circuit operable to identify and unpack the one or more input data units based on the header and the payload of each of the one or more input data units; and
an output port operable to transmit one or more output data units comprising the unpacked one or more input data units, once per clock cycle.
2. The structure of claim 1 , further comprising a first stage pipeline register operable to rotate the plurality of packed bits of the one or more input data units.
3. The structure of claim 2 , further comprising a second stage pipeline register operable to determine the length of the payload of each of the rotated one or more input data units based on the header of each of the rotated one or more input data units.
4. The structure of claim 3 , further comprising a decode and decompress unit operable to unpack the one or more input data units based on the determined length of the payload of each of the one or more input data units.
5. The structure of claim 3 , further comprising a length lookahead unit operable to determine a length of a payload of a next input data unit of the rotated one or more input data units based on a determined length of a payload of a current input data unit of the rotated one or more input data units.
6. The structure of claim 1 , further comprising:
a 192-bit buffer operable to receive the one or more input data units; and
a read pointer register operable to indicate a starting point of the one or more input data units in the 192-bit buffer.
7. The structure of claim 6 , further comprising:
a 0-to-63-bit shifter operable to shift the one or more input data units based on the starting point of the one or more input data units; and
a length decoder operable to determine a length of a payload of a current input data unit of the shifted one or more input data units based on a header of the current input data unit.
8. The structure of claim 7 , further comprising:
a next read pointer adder operable to determine a next read pointer which indicates a next starting point of the one or more input data units in the 192-bit buffer based on the starting point of the one or more input data units and the determined length of the payload of the current input data unit; and
a 64-bit or 128-bit preshifter operable to shift the one or more input data units in the 192-bit buffer based on the next starting point of the one or more input data units.
9. The structure of claim 8 , wherein:
the next starting point of the one or more input data units is greater than a 127 th bit in the 192-bit buffer; and
the 64-bit or 128-bit preshifter shifts the one or more input data units in the 192-bit buffer by 128 bits.
10. The structure of claim 8 , wherein:
the next starting point of the one or more input data units is greater than a 63 rd bit and less than a 128 th bit, in the 192-bit buffer; and
the 64-bit or 128-bit preshifter shifts the one or more input data units in the 192-bit buffer by 64 bits.
11. A structure for unpacking a variable number of data bits, comprising:
an input port operable to receive one or more input data units comprising a plurality of packed bits of data, each of the one or more input data units comprising a header and a payload, the header comprising a predetermined number of bits and identifying a format of the payload and a length of the payload, and the payload comprising a variable number of bits;
a first stage pipeline register operable to rotate the plurality of packed bits of the one or more input data units;
a second stage pipeline register operable to determine the length of the payload of each of the rotated one or more input data units based on the header of each of the rotated one or more input data units;
a decode and decompress unit operable to unpack the one or more input data units based on the determined length of the payload of each of the one or more input data units; and
an output port operable to transmit one or more output data units comprising the unpacked one or more input data units, once per clock cycle.
12. The structure of claim 11 , further comprising:
a length lookahead unit operable to determine a length of a payload of a next input data unit of the rotated one or more input data units based on a determined length of a payload of a current input data unit of the rotated one or more input data units; and
an adder operable to increment a head pointer register by the determined length of the payload of the next input data unit such that the head pointer register indicates a starting point of the one or more input data units in the first stage pipeline register.
13. A method of unpacking a variable number of data bits, comprising:
receiving one or more input data units comprising a plurality of packed bits of data, each of the one or more input data units comprising a header and a payload, the header comprising a predetermined number of bits and identifying a format of the payload and a length of the payload, and the payload comprising a variable number of bits;
identifying and unpacking the one or more input data units based on the header and the payload of each of the one or more input data units; and
transmitting one or more output data units comprising the unpacked one or more input data units, once per clock cycle.
14. The method of claim 13 , further comprising rotating the plurality of packed bits of the one or more input data units.
15. The method of claim 14 , further comprising determining the length of the payload of each of the rotated one or more input data units based on the header of each of the rotated one or more input data units.
16. The method of claim 15 , further comprising unpacking the one or more input data units based on the determined length of the payload of each of the one or more input data units.
17. The method of claim 15 , further comprising determining a length of a payload of a next input data unit of the rotated one or more input data units based on a determined length of a payload of a current input data unit of the rotated one or more input data units.
18. The method of claim 13 , further comprising indicating a starting point of the one or more input data units in a 192-bit buffer.
19. The method of claim 18 , further comprising:
shifting the one or more input data units based on the starting point of the one or more input data units; and
determining a length of a payload of a current input data unit of the shifted one or more input data units based on a header of the current input data unit.
20. The method of claim 19 , further comprising:
determining a next read pointer which indicates a next starting point of the one or more input data units in the 192-bit buffer based on the starting point of the one or more input data units and the determined length of the payload of the current input data unit; and shifting the one or more input data units in the 192-bit buffer based on the next starting point of the one or more input data units.