Ternary and multi-value digital signal scramblers, decramblers and sequence generators
Reversible and self reversing multi-value scrambling functions created by applying multi-value inverters are disclosed. The generation of possible multi-value inverters is also presented. Corresponding multi-value descrambling functions are also disclosed. The multi-value functions are used in circuits that scramble and descramble multi-value signals. The multi-value functions can also be used in signal generators. Such signal generators do not require the use of multipliers. The auto-correlation of the signals generated by the signal generators is also presented. Electronic circuits that implement the multi-value functions are also described.
1. A device to generate on an output an n-state symbol, the n-state symbol having one of n states with n>2 and the n-state symbol being represented by a signal, comprising:
a first input and a second input to a memory, each input enabled to receive a signal representing a first and a second n-state symbol each provided by an n-state shift register;
the memory storing a non-commutative n by n n-state truth table not being a modulo-n subtraction; and
an output of the memory to provide a signal representing the n-state symbol in accordance with the non-commutative n by n truth table.
2. The device of claim 1 , wherein n>3.
3. The device of claim 1 , wherein the non-commutative n by n truth table represents a truth table of an addition over a finite field GF(n) modified in accordance with an n-state multiplication over GF(n).
4. The device of claim 1 , wherein the non-commutative n by n truth table represents a commutative n by n truth table modified in accordance with an n-state inverter.
5. The device of claim 1 , wherein the device is part of a scrambler.
6. The device of claim 1 , wherein the device is part of a descrambler.
7. The device of claim 6 , wherein the descrambler is self-synchronizing.
8. The device of claim 1 , wherein the device is part of a generator of a sequence of n state symbols.
9. The device of claim 8 , wherein the sequence is a maximum-length sequence.
10. The device of claim 1 , wherein an n-state symbol is represented by a plurality of binary signals.
11. The device of claim 1 , wherein the device is part of a communication system.
12. A method to generate with a processor an n-state symbol as part of processing a sequence of n-state symbols, each n-state symbol having one of n states with n>2 and being represented by a signal, comprising:
the processor storing on a memory device in a coder a non-commutative n by n n-state truth table not being a modulo-n subtraction;
the processor inputting on a first input of the memory device a signal representing a first n-state symbol;
the processor inputting on a second input of the memory device a signal representing a second n-state symbol; and
outputting on an output of the memory device a signal representing the n-state symbol generated in accordance with the non-commutative n by n n-state truth table.
13. The method of claim 12 , wherein n>3.
14. The method of claim 12 , wherein the non-commutative n by n n-state truth table represents a truth table of an addition over a finite field GF(n) modified in accordance with an n-state multiplication over GF(n).
15. The method of claim 12 , wherein the non-commutative n by n n-state truth table represents a commutative n by n truth table modified in accordance with an n-state inverter.
16. The method of claim 12 , further comprising:
processing the n-state symbol in a Linear Feedback Shift Register (LFSR).
17. The method of claim 12 , further comprising:
processing the n-state symbol in a descrambler.
18. The method of claim 12 , wherein the n-state symbol is generated in a sequence generator.
19. The method of claim 12 , wherein the n-state symbol is generated in a communication system.
20. The method of claim 12 , wherein the n-state symbol is represented by a plurality of binary symbols.