Method and system to improve the operations of an integrated non-transparent bridge device

1. An apparatus comprising:

a non-transparent bridge coupled with a device via a Root Port; and

logic coupled with the non-transparent bridge to maintain an order of a plurality of interrupt signals to be sent to the device via the Root Port, wherein the logic is to:

determine whether a doorbell transaction is next to be popped from a transmission queue;

determine whether a doorbell register associated with the doorbell transaction has been updated; and

generate one of the plurality of interrupt signals in response to a determination that the doorbell transaction is next to be popped from the transmission queue and a determination that the doorbell register associated with the doorbell transaction has been updated.

2. The apparatus of claim 1 , wherein the plurality of interrupt signals comprises at least one of a legacy interrupt, a message signal interrupt (MSI), and an extended MSI (MSI-X).

3. The apparatus of claim 1 , further comprising a plurality of configuration registers, wherein the doorbell register is one of a plurality of configuration registers.

4. The apparatus of claim 3 , wherein the plurality of configuration registers comprises a mapping register, and wherein the mapping register is to indicate a mapping of each bit of the doorbell register with a respective one of a plurality of MSI-X vectors.

5. The apparatus of claim 1 , wherein the apparatus is operable in accordance with Peripheral Component Interface Express (PCIe) specification.

6. The apparatus of claim 1 , further comprising a processing core, wherein the logic is part of the processing core.

7. The apparatus of claim 6 , further comprising:

a memory coupled with the processing core and the non-transparent bridge, wherein the processing core is to allocate a contiguous portion of the memory, the contiguous portion of the memory comprising a primary base address register associated with the non-transparent bridge and a secondary base address register associated with the device.

8. A system comprising:

a memory;

a processing core;

a root complex coupled with the processing core, the memory, and a bus;

a port on the bus to operate as a non-transparent bridge, the non-transparent bridge to be coupled with a device having a Root Port via a communication link, wherein the processing core is to map a secondary side of the non-transparent bridge associated with the device into a memory mapped input output (MMIO) region of the memory associated with a primary side of the non-transparent bridge by allocating a contiguous region of the memory for a primary base address register and a secondary base address register;

interrupt generation logic coupled with the non-transparent bridge to maintain an order of a plurality of interrupt signals to be sent to the device via the communication link;

a plurality of configuration registers, and wherein the interrupt generation logic to maintain the order of the plurality of interrupt signals to be sent to the device via the communication link is to:

determine whether a doorbell transaction is next to be popped from a transmission queue;

determine whether a doorbell register associated with the doorbell transaction has been updated; and

generate one of the plurality of interrupt signals in response to a determination that the doorbell transaction is next to be popped from the transmission queue and a determination that the doorbell register associated with the doorbell transaction has been updated.

9. The system of claim 8 , wherein the processing core is further to report a size of the primary base address register as a size of the contiguous region of the memory.

10. The system of claim 8 , wherein the device is one of another non-transparent bridge device and Root Port device.

11. The system of claim 8 , wherein the plurality of configuration registers comprises a mapping register, and wherein the mapping register is to indicate a mapping of each bit of the doorbell register with a respective one of a plurality of vectors.

12. The system of claim 8 , wherein the plurality of vectors comprises at least one of a legacy interrupt, a message signal interrupt (MSI), and an extended MSI (MSI-X).

13. The system of claim 12 , wherein the system is operable in accordance with Peripheral Component Interface Express (PCIe) specification.

14. A method comprising:

facilitating dynamic modification of a mapping of each bit of a doorbell register with a respective one of a plurality of vectors, wherein the mapping is based at least in part on a mapping register;

maintaining an order of a plurality of interrupt signals to be sent to a device via a Root Port;

wherein maintaining the order of the plurality of interrupt signals to be sent to the device via the Root Port comprises:

determining whether a doorbell transaction is next to be popped from a transmission queue;

determining whether a doorbell register associated with the doorbell transaction has been updated; and

generating one of the plurality of interrupt signals in response to a determination that the doorbell transaction is next to be popped from the transmission queue and a determination that the doorbell register associated with the doorbell transaction has been updated.

15. The method of claim 14 , wherein the mapping register comprises one or more bits associated with each bit of the doorbell register, further comprising:

programming the one or more bits associated with each bit of the doorbell register to set the mapping of each bit of the doorbell register with the respective one of the plurality of vectors.

16. The method of claim 15 , wherein the plurality of vectors comprises at least one of a legacy interrupt, a message signal interrupt (MSI), and an extended MSI (MSI-X).

17. The method of claim 14 , further comprising:

indicating a size of a primary base address register as a sum of a size of the primary base address register and a size of a secondary base address register.