Method for manufacturing semiconductor device having a metal gate electrode
Example embodiments relate to a method for manufacturing a semiconductor device, wherein a metal gate electrode therein may be formed without a void in a lower portion of the metal gate electrode. The method may include providing a substrate, forming a dummy gate electrode on the substrate, forming a gate spacer on the substrate to be contiguous to the dummy gate electrode, forming a first recess by simultaneously removing a portion of the dummy gate electrode and a portion of the gate spacer, the first recess having an upper end wider than a lower end, forming a second recess by removing the dummy gate electrode remaining after forming the first recess, and forming a metal gate electrode by depositing a metal to fill the first and second recesses.
1. A method for manufacturing a semiconductor device, the method comprising:
forming a barrier film pattern and a dummy gate electrode on a substrate;
forming a gate spacer on a sidewall of the dummy gate electrode;
forming a first recess
by simultaneously removing
a portion of the dummy gate electrode and
a portion of the gate spacer,
the first recess having an upper end wider than a lower end;
forming a second recess by removing the dummy gate electrode remaining after forming the first recess; and
etching the gate spacer after forming the second recess so that widths of the first and second recesses gradually increase from a lower portion of the second recess to an upper portion of the first recess; and
forming a metal gate electrode by depositing a metal on the barrier film pattern to fill the first and second recesses.
2. The method of claim 1 , wherein the forming a first recess includes plasma-based dry etching.
3. The method of claim 2 , wherein the plasma-based dry etching is performed in a plasma chamber in which a bias voltage applied to the substrate is substantially zero.
4. The method of claim 2 , wherein the plasma-based dry etching is performed using a combination gas of HBr, NF 3 , and Cl 2 .
5. The method of claim 1 , wherein the forming a second recess includes NH 4 OH-based wet etching.
6. The method of claim 1 , wherein the etching the gate spacer is performed by plasma-based dry etching using a source gas having a higher etch selectivity to the gate spacer than to the barrier film pattern.
7. The method of claim 6 , wherein the plasma-based dry etching is performed in a plasma chamber in which a bias voltage applied to the substrate is substantially zero.
8. The method of claim 6 , wherein the plasma-based dry etching is performed using a combination of HBr, NF 3 , and Cl 2 as a source gas.
9. The method of claim 8 , wherein a slope of the gate spacer is adjusted by adjusting a composition ratio of NF 3 and HBr.
10. The method of claim 6 , wherein a slope of the gate spacer is adjusted by adjusting a duration of time in which the plasma-based dry etching is performed.
11. The method of claim 10 , wherein the barrier film pattern includes titanium nitride.
12. The method of claim 1 , further comprising:
forming a gate insulation film pattern made of a high dielectric constant (high-k) material on the substrate, wherein the barrier film pattern is formed on the gate insulation film pattern.
13. The method of claim 1 , wherein the forming a barrier film pattern includes the barrier film pattern being formed before the dummy gate electrode.
14. The method of claim 1 , wherein the forming a second recess includes etching the dummy gate electrode while retaining an integrity of the barrier film pattern.
15. The method of claim 1 , further comprising:
forming a gate insulation film pattern on the substrate, the gate insulation film pattern being formed before the barrier film pattern.