Circuit including a negative differential resistance (NDR) device having a graphene channel, and method of operating the circuit

1. A circuit comprising:

a first circuit portion including a resistance; and

a second circuit portion including:

a three-terminal negative differential resistance (NDR) device which includes a gate, a graphene channel and source and drain electrodes contacting the graphene channel; and

a gate voltage source which modulates a gate voltage on the gate such that an electric current through the graphene channel exhibits negative differential resistance which cancels out at least a portion of the resistance of the first circuit portion.

2. The circuit of claim 1 , wherein the NDR device further comprises:

a gate dielectric contacting the gate, the graphene channel contacting the gate dielectric,

wherein the source and drain electrodes contact the gate dielectric.

3. The circuit of claim 2 , further comprising:

a bias voltage source which modulates a bias voltage between the source and drain electrodes.

4. The circuit of claim 3 , wherein the bias voltage comprises a range of bias voltages, and the gate voltage source modulates the gate voltage on the gate such that the electric current through the graphene channel exhibits negative differential resistance over the range of bias voltages.

5. The circuit of claim 3 , wherein the gate voltage source modulates the gate voltage on the gate to be in a range from −10V to 10V.

6. The circuit of claim 3 , wherein the bias voltage source modulates the bias voltage between the source and drain electrodes to be in a range from −10V to 10V.

7. The circuit of claim 3 , wherein the gate voltage source modulates the gate voltage such that the gate voltage satisfies the following:

V

G

2

>

8

⁢

(

σ

min

C

·

μ

)

2

Eq

.

⁢

(

5

)

where:

σ min is a minimum conductivity of the graphene channel of the NDR device;

C is a capacitance of the gate; and

μ is a mobility of carriers in the graphene channel.

8. The circuit of claim 3 , wherein a conductivity, σ, of the graphene channel is given by Equation (1):

σ

=

K

⁡

[

(

V

G

-

V

NP

)

2

+

(

σ

min

K

)

2

]

1

/

2

Eq

.

⁢

(

1

)

where:

K is a slope factor which is given by K=C·μ (C being a capacitance of the gate, and μ being a mobility of carriers in the graphene channel);

V G is gate voltage;

σ min is a minimum conductivity of the graphene channel; and

V NP is gate voltage corresponding to the minimum conductivity of the graphene channel, and is given by: V NP =V NP 0 +V DS /2, where V DS is source-drain bias voltage, and V NP 0 is a gate voltage of minimal current when V DS approaches zero.

9. The circuit of claim 8 , wherein for σ min /K=0.5, an output conductance, g DS , of the graphene channel is negative.

10. The circuit of claim 2 , wherein a thickness of the gate dielectric, a dielectric constant of the gate dielectric and a carrier mobility of the graphene channel are such that the NDR device exhibits a negative differential resistance.

11. The circuit of claim 2 , wherein a thickness of the gate dielectric is in a range from 0.5 nm to 50 nm, a dielectric constant of the gate dielectric is in a range from 2 to 50, and a carrier mobility of the graphene channel is in a range from 100 (cm 2 /Vs) to 1 million (cm 2 /Vs).

12. The circuit of claim 2 , wherein the gate dielectric comprises at least one of aluminum oxide, hafnium oxide, silicon oxide, yttrium oxide and zirconium oxide, SrO, CaO, HfSiO 4 and ZrSiO 4 .

13. The circuit of claim 1 , wherein the circuit comprises one of an amplifier circuit, an oscillator circuit, a mixer circuit, an impedance cancellation circuit, a memory circuit and a logic circuit.

14. The circuit of claim 1 , wherein the NDR device comprises one of a back gate configuration and a front gate configuration.

15. A method of operating a circuit, the method comprising:

providing a first circuit portion including a resistance, and a second circuit portion including a three-terminal negative differential resistance (NDR) device which includes a gate, a graphene channel and source and drain electrodes contacting the graphene channel,

modulating a gate voltage on the gate such that an electric current through the graphene channel exhibits negative differential resistance which cancels out at least a portion of the resistance of the first circuit portion.

16. The method of claim 15 , wherein the NDR device further comprises a gate dielectric contacting the gate, the graphene channel contacting the gate dielectric,

wherein the source and drain electrodes contact the gate dielectric, and the circuit comprises the NDR device, a gate voltage source and a bias voltage source, and

wherein the method further comprises:

modulating a bias voltage between the source and drain electrodes, by using the bias voltage source.

17. The method of claim 16 , wherein the bias voltage comprises a range of bias voltages, and the gate voltage source modulates the gate voltage on the gate such that the electric current through the graphene channel exhibits negative differential resistance over the range of bias voltages.

18. The method of claim 15 , wherein the gate voltage satisfies the following:

V

G

2

>

8

⁢

(

σ

min

C

·

μ

)

2

Eq

.

⁢

(

5

)

where:

σ min is a minimum conductivity of the graphene channel of the NDR device;

C is a capacitance of the gate; and

μ is a mobility of carriers in the graphene channel.

19. The method of claim 18 , wherein a conductivity, σ, of the graphene channel is given by Equation (1):

σ

=

K

⁡

[

(

V

G

-

V

NP

)

2

+

(

σ

min

K

)

2

]

1

/

2

Eq

.

⁢

(

1

)

where:

K is a slope factor which is given by K=C·μ (C being a capacitance of the gate, and μ being a mobility of carriers in the graphene channel);

V G is gate voltage;

σ min is a minimum conductivity of the graphene channel; and

V NP is gate voltage corresponding to the minimum conductivity of the graphene channel, and is given by: V NP =V NP 0 +V DS /2, where V DS is source-drain bias voltage, and V NP 0 is a gate voltage of minimal current when V DS approaches zero.

20. The method of claim 19 , wherein for σ min /K=0.5, an output conductance, g DS , of the graphene channel is negative.

21. A circuit comprising:

a negative differential resistance (NDR) device comprising:

a gate;

a graphene channel including a carrier mobility in a range from 100 (cm 2 /Vs) to 1 million (cm 2 /Vs);

a gate dielectric contacting the gate and including a thickness in a range from 0.5 nm to 50 nm and a dielectric constant in a range from 2 to 50, the graphene channel contacting the gate dielectric; and

source and drain electrodes contacting the gate dielectric and the graphene channel;

a gate voltage source which modulates a gate voltage on the gate such that an electric current through the graphene channel exhibits negative differential resistance; and

a bias voltage source which modulates a bias voltage between the source and drain electrodes,

wherein the bias voltage comprises a range of bias voltages, and the gate voltage source modulates the gate voltage on the gate such that the electric current through the graphene channel exhibits negative differential resistance over the range of bias voltages, and

wherein the gate voltage source modulates the gate voltage such that the gate voltage satisfies the following:

V

G

2

>

8

⁢

(

σ

min

C

·

μ

)

2

Eq

.

⁢

(

5

)

where:

σ min is a minimum conductivity of the graphene channel of the NDR device;

C is a capacitance of the gate; and

μ is a mobility of carriers in the graphene channel.

22. The circuit of claim 21 , wherein a conductivity, σ, of the graphene channel is given by Equation (1):

σ

=

K

⁡

[

(

V

G

-

V

NP

)

2

+

(

σ

min

K

)

2

]

1

/

2

Eq

.

⁢

(

1

)

where:

K is a slope factor which is given by K=C·μ (C being a capacitance of the gate, and μ being a mobility of carriers in the graphene channel);

V G is gate voltage;

σ min is a minimum conductivity of the graphene channel; and

V NP is gate voltage corresponding to the minimum conductivity of the graphene channel, and is given by: V NP =V NP 0 +V DS /2, where V DS is source-drain bias voltage, and V NP 0 is a gate voltage of minimal current when V DS approaches zero.

23. The circuit of claim 22 , wherein for σ min /K=0.5, an output conductance, g DS , of the graphene channel is negative.

24. A method of operating a circuit which includes a negative differential resistance (NDR) device which includes a gate and a graphene channel, and a gate voltage source, the method comprising:

modulating a gate voltage on the gate such that an electric current through the graphene channel exhibits negative differential resistance,

wherein the NDR device further comprises a gate dielectric contacting the gate, the graphene channel contacting the gate dielectric, and source and drain electrodes contacting the gate dielectric and the graphene channel,

wherein a thickness of the gate dielectric is in a range from 0.5 nm to 50 nm, a dielectric constant of the gate dielectric is in a range from 2 to 50, and a carrier mobility of the graphene channel is in a range from 100 (cm 2 /Vs) to 1 million (cm 2 /Vs),

wherein the circuit further comprises a bias voltage source which modulates a bias voltage between the source and drain electrodes,

wherein the bias voltage comprises a range of bias voltages, and the gate voltage source modulates the gate voltage on the gate such that the electric current through the graphene channel exhibits negative differential resistance over the range of bias voltages, and

wherein the gate voltage source modulates the gate voltage such that the gate voltage satisfies the following:

V

G

2

>

8

⁢

(

σ

min

C

·

μ

)

2

Eq

.

⁢

(

5

)

where:

σ min is a minimum conductivity of the graphene channel of the NDR device;

C is a capacitance of the gate; and

μ is a mobility of carriers in the graphene channel.