IP Library Granted Patent US 8,607,072
Granted Patent B2
US 8,607,072 · App. 13/094,093 · Granted Dec 10, 2013

Storage device content authentication

Inventors: Xuemin Chen (Rancho Sante Fe, CA); Steve W. Rodgers (San Diego, CA); Iue-Shuenn I. Chen (San Diego, CA); Francis Cheung (Del Mar, CA)
Assignee: Broadcom Corporation
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Quick Facts
Patent No.
US 8,607,072
App. No.
13/094,093
Granted
Dec 10, 2013
Kind
B2
Abstract

Systems and methods that support storage device content authentication are provided. A system that verifies storage device content received from a storage device may comprise, for example, a security processor coupled to the storage device. The security processor may be adapted to receive a partitioned storage device region from the storage device. The partitioned storage device region may comprise, for example, regional content and first hashed regional content. The security processor may generate, for example, second hashed regional content by performing a hashing function on the regional content received by the security processor. The security processor may compare, for example, the first hashed regional content to the second hashed regional content. The security processor may verify the regional content received by the security processor if the first hashed regional content is the same as the second hashed regional content.

Claims (26)

1. A method for verifying content, comprising:

partitioning storage device content into a plurality of storage device regions, each storage device region comprising a potential instruction region and a first region, the potential instruction region including executable instructions and data, the first region including a first hash of the potential instruction region;

receiving, by a security processor, a particular storage device region, the security processor comprising a memory;

generating a second hashed regional content by performing a single hashing function on the potential instruction region that includes the executable instructions of the particular storage device region received by the security processor;

comparing the first hash of the potential instruction region of the particular storage device region to the second hashed regional content;

executing, by a host processor that is part of a system on a chip, the executable instructions of the potential instruction region of the particular storage device region if the first hash of the potential instruction region of the particular storage device region is the same as the second hashed regional content; and

preventing access, by the host processor, to the potential instruction region of the particular storage device region received by the security processor if the first hash of the potential instruction region of the particular storage region is not the same as the second hashed regional content.

2. The method according to claim 1 , wherein the first hash of the potential instruction region of the particular storage device region comprises a first hash value, wherein the second hashed regional content comprises a second hash value, and wherein the first hash value is compared to the second hash value.

3. The method according to claim 1 , wherein the host processor, the security processor and a second memory that stores the storage device content are connected via one or more buses in a single device.

4. The method according to claim 1 , wherein the storage device content comprises at least one of the following: flash memory content, RAM content and SDRAM content.

5. The method according to claim 1 , further comprising cryptographically signing the particular storage device region.

6. The method according to claim 5 , wherein the cryptographically signing comprises applying at least one of a private key and a public key over the particular storage device region.

7. The method according to claim 5 , further comprising decrypting the cryptographically signed storage device region.

8. The method according to claim 7 , wherein the decrypting comprises applying at least one of a private key and a public key over the cryptographically signed storage device region.

9. The method according to claim 1 , wherein the generating comprises generating a second hashed regional content by performing a one-way hashing function on the potential instruction region of the particular storage device region received by the security processor.

10. The method according to claim 1 , wherein the generating comprises generating a second hashed regional content by performing a secure hash algorithm.

11. The method according to claim 1 , further comprising causing an exception if the first hash of the potential instruction region of the particular storage device region is not the same as the second hashed regional content.

12. The method according to claim 1 , further comprising setting a fail bit in a register if the first hash of the potential instruction region of the particular storage device region is not the same as the second hashed regional content.

13. The method according to claim 1 , further comprising repeatedly performing at least the generating, the comparing, the executing, and the preventing access.

14. The method according to claim 1 , further comprising performing the generating, the comparing, the executing, and the preventing access concurrently for at least two storage device regions.

15. The method according to claim 1 , further comprising repeatedly performing the generating, the comparing, the executing, and the preventing access concurrently for at least two storage device regions.

16. The method according to claim 1 , further comprising periodically performing the generating, the comparing, the executing, and the preventing access for respective storage device regions.

17. The method according to claim 1 , wherein the potential instruction region is defined inside a read only memory.

18. The method according to claim 1 , wherein the security processor comprises a public key engine or a random number generator.

19. The method according to claim 1 , wherein the security processor comprises a one-way hasher.

20. The method according to claim 1 , wherein an authentication algorithm executed by the security processor is stored in a read only memory.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER IN THE INCORRECT US PATENT NO. 8,876,094 PREVIOUSLY RECORDED ON REEL 047351 FRAME 0384. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 049248/0558 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF THE MERGER PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0910. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047351/0384 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0910 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 13, 2012
From: CHEN, SHERMAN (XUEMIN); RODGERS, STEVE W.; CHEN, IUE-SHUENN I.; CHEUNG, FRANCIS CHI-WAI
To: BROADCOM CORPORATION
Reel/Frame 027851/0544 →
Continuity (2)
Continuation 10913197 · Aug 6, 2004
Related Publication 20110202776A1 · Aug 18, 2011