Power MOSFET with integrated gate resistor and diode-connected MOSFET

1. A semiconductor device, comprising:

a semiconductor substrate;

a power metal oxide semiconductor field effect transistor (MOSFET), including:

a power MOSFET gate structure disposed on said substrate;

a body region of a first conductivity type disposed in said substrate under said power MOSFET gate structure;

a source region of a second conductivity type opposite from said first conductivity type; and

a drain region of said second conductivity type;

a diode-connected MOSFET proximate to said power MOSFET, including:

a gate structure disposed on said substrate;

a source region of said second conductivity type;

a drain region of said second conductivity type; and

a body region of said first conductivity type disposed in said substrate under said diode-connected MOSFET gate structure; and

metal interconnects, so that:

a gate input node of said semiconductor device is electrically coupled to said drain region of said diode-connected MOSFET;

said gate input node is electrically coupled through a shunt resistor to said power MOSFET gate structure and said diode-connected MOSFET drain region;

a drain input/output node of said semiconductor device is electrically coupled to said power MOSFET drain region; and

a source input/output node of said semiconductor device is electrically coupled to said power MOSFET source region;

so that said diode-connected MOSFET source region is electrically isolated from said power MOSFET source region by a pn junction and said diode-connected MOSFET drain region is electrically isolated from said power MOSFET source region by a pn junction.

2. The semiconductor device of claim 1 , in which said first conductivity type is p-type, said second conductivity type is n-type, and said power MOSFET and said diode-connected MOSFET are n-channel transistors.

3. The semiconductor device of claim 1 , in which:

said substrate has said first conductivity type;

said power MOSFET drain region is disposed at a top surface of said substrate;

said drain input/output node makes electrical connection to said power MOSFET drain region at said substrate top surface;

said power MOSFET source region is disposed at a top surface of said substrate;

said power MOSFET source region is electrically coupled to a power MOSFET source contact region disposed at a bottom surface of said substrate; and

said source input/output node makes electrical connection to said power MOSFET source contact region at said substrate bottom surface.

4. The semiconductor device of claim 1 , in which:

said substrate has said second conductivity type;

said power MOSFET source region is disposed at a top surface of said substrate;

said source input/output node makes electrical connection to said power MOSFET source region at said substrate top surface;

said power MOSFET drain region is disposed at a top surface of said substrate;

said power MOSFET drain region is electrically coupled to a power MOSFET drain contact region disposed at a bottom surface of said substrate; and

said drain input/output node makes electrical connection to said power MOSFET drain contact region at said substrate bottom surface.

5. The semiconductor device of claim 1 , in which a field plate overlaps said power MOSFET drain region and said diode-connected MOSFET drain region.

6. The semiconductor device of claim 1 , further including heavily doped breakdown layers having said first conductivity type disposed at a lower boundary of said diode-connected MOSFET source region and at a lower boundary of said diode-connected MOSFET drain region.

7. The semiconductor device of claim 1 , in which:

an effective gate length of said power MOSFET, corresponding to a lateral distance between said power MOSFET source region and said power MOSFET drain region, is 0.3 to 1 micron; and

an effective gate length of said diode-connected MOSFET, corresponding to a lateral distance between said diode-connected MOSFET source region and said diode-connected MOSFET drain region, is 0.5 to 2 microns.

8. The semiconductor device of claim 1 , in which said diode connected MOSFET is a first diode connected MOSFET, and further including a second diode connected MOSFET, in which said first diode connected MOSFET and said second diode connected MOSFET are disposed at a periphery of said power MOSFET.

9. A process of forming a semiconductor device, comprising the steps of:

providing a semiconductor substrate;

concurrently forming a gate structure of a power MOSFET over said substrate and a gate structure for a diode-connected MOSFET over said substrate;

forming at least one body region in said substrate in at least an area defined for said power MOSFET, said body region having a first conductivity type;

forming a drain region of said power MOSFET in said substrate, said power MOSFET drain region having a second conductivity type opposite from said first conductivity type;

forming a source region of said power MOSFET in said substrate, said power MOSFET source region having said second conductivity type;

forming a source region of said diode-connected MOSFET in said substrate, said diode-connected MOSFET source region having said second conductivity type;

forming a drain region of said diode-connected MOSFET in said substrate, said diode-connected MOSFET drain region having said second conductivity type;

so that said diode-connected MOSFET source region is electrically isolated from said power MOSFET source region by a pn junction and said diode-connected MOSFET drain region is electrically isolated from said power MOSFET source region by a pn junction; and

forming metal interconnects, so that:

a gate input node of said semiconductor device is electrically coupled to said diode-connected MOSFET source region;

said gate input node is electrically coupled through a shunt resistor to said power MOSFET gate structure and said diode-connected MOSFET drain region;

a drain input/output node of said semiconductor device is electrically coupled to said power MOSFET drain region; and

a source input/output node of said semiconductor device is electrically coupled to said power MOSFET source region.

10. The process of claim 9 , in which said first conductivity type is p-type, said second conductivity type is n-type, and said power MOSFET and said diode-connected MOSFET are n-channel transistors.

11. The process of claim 9 , in which:

said substrate has said first conductivity type;

said process includes forming a power MOSFET source contact region having said first conductivity type disposed at a bottom surface of said substrate;

said process includes forming a sinker having said first conductivity type so that said sinker provides an electrical connection between said power MOSFET source region and said power MOSFET source contact region;

said drain input/output node makes electrical connection to said power MOSFET drain region at said substrate top surface; and

said source input/output node makes electrical connection to said power MOSFET source contact region at said substrate bottom surface.

12. The process of claim 9 , in which:

said substrate has said second conductivity type;

said power MOSFET drain region is disposed at a top surface of said substrate;

said process includes forming a power MOSFET drain contact region having said second conductivity type disposed at a bottom surface of said substrate, so that said power MOSFET drain region is electrically coupled to said power MOSFET drain contact region through said substrate;

said power MOSFET source region is disposed at a top surface of said substrate;

said source input/output node makes electrical connection to said power MOSFET source region at said substrate top surface; and

said drain input/output node makes electrical connection to said power MOSFET drain contact region at said substrate bottom surface.

13. The process of claim 9 , in which a field plate overlaps said power MOSFET drain region and said diode-connected MOSFET drain region.

14. The process of claim 9 , further including forming heavily doped breakdown layers having said first conductivity type disposed at a lower boundary of said diode-connected MOSFET source region and at a lower boundary of said diode-connected MOSFET drain region.

15. The process of claim 9 , in which:

an effective gate length of said power MOSFET, corresponding to a lateral distance between said power MOSFET source region and said power MOSFET drain region, is 0.3 to 1 micron; and

an effective gate length of said diode-connected MOSFET, corresponding to a lateral distance between said diode-connected MOSFET source region and said diode-connected MOSFET drain region, is 0.5 to 2 microns.

16. The process of claim 9 , in which said diode-connected MOSFET is a first diode-connected MOSFET, and further including the steps of:

forming a source region of a second diode-connected MOSFET and a drain region of said second diode-connected MOSFET in said substrate concurrently with said first diode-connected MOSFET source region and drain region, said second diode-connected MOSFET source region and drain region having said second conductivity type, said second diode-connected MOSFET being located proximate to said power MOSFET, so that said second diode-connected MOSFET source region is electrically isolated from said power MOSFET source region by a pn junction and said second diode-connected MOSFET drain region is electrically isolated from said power MOSFET source region by a pn junction;

forming a gate structure of said second diode-connected MOSFET over said substrate concurrently with said first diode-connected MOSFET gate structure; and

forming said metal interconnects so that:

said gate input node of said semiconductor device is electrically coupled to said second diode-connected MOSFET drain region; and

said gate input node is electrically coupled through a second shunt resistor to said power MOSFET gate structure and said second diode-connected MOSFET drain region.