Vertically-integrated nonvolatile memory devices having laterally-integrated ground select transistors
Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines.
1. A nonvolatile memory device comprising:
a plurality of common source lines provided in a substrate having a first conductive type, extended in a first direction to be separated from each other, and having a second conductive type different from the first conductive type;
a substrate channel region provided on the substrate between the common source lines, and comprising edge regions directly adjacent to the common source lines and a middle region between the edge regions; and
a plurality of vertical channels vertically provided from the substrate channel region,
wherein the edge regions have an impurity doping concentration different from the middle region.
2. The nonvolatile memory device of claim 1 , wherein:
the edge regions and the middle region have the first conductive type, and
the impurity doping concentration of the edge regions is higher than that of the middle region.
3. The nonvolatile memory device of claim 1 , wherein the middle region comprises:
first regions contacting the vertical channels, and extended in the first direction, and
a second region extended in the first direction between the first regions.
4. The nonvolatile memory device of claim 3 , wherein:
the first regions have the first conductive type of a first concentration lower than the impurity doping concentration of the edge regions, and
the second region has the first conductive type of a second concentration lower than the first concentration.
5. The nonvolatile memory device of claim 3 , wherein:
the first regions have the first conductive type of a first concentration lower than the impurity doping concentration of the edge regions, and
the second region has the second conductive type.
6. The nonvolatile memory device of claim 1 , wherein the edge regions are provided between the common source lines and a vertical channel most adjacent to the common source lines.
7. The nonvolatile memory device of claim 1 , wherein:
the vertical channels are arranged in a matrix type based on the first direction and a second direction intersecting the first direction, and
at least three vertical channels are arranged in the second direction, between the common source lines.
8. The nonvolatile memory device of claim 7 , wherein the vertical channels arranged in the first direction are electrically coupled to one selection line extended in the first direction.
9. The nonvolatile memory device of claim 1 , wherein the vertical channels directly adjacent to each other are alternately offset.
10. The nonvolatile memory device of claim 9 , wherein the vertical channels, which are directly adjacent to each other and are alternately offset, are electrically coupled to one selection line extended in the first direction.
11. The nonvolatile memory device of claim 10 , further comprising:
a plurality of conductive patterns stacked on the substrate to be separated from each other, wherein the vertical channels pass through the conductive patterns; and
an information storage layer provided between the vertical channels and the conductive patterns,
wherein the substrate channel region serves as a lateral channel of a lowermost conductive pattern.