Methods of designing semiconductor devices and methods of modifying layouts of semiconductor devices
In a method of designing a semiconductor device, a transistor included in a layout of the semiconductor device may be selected. A biasing data may be set for changing a characteristic of the selected transistor. A design rule check (DRC) process for the layout of the semiconductor device may be performed after ignoring the biasing data. An optical proximity correction (OPC) process for the layout of the semiconductor device may be performed based on the biasing data.
1. A method of designing a semiconductor device, the method comprising:
selecting a transistor included in a layout of the semiconductor device;
setting biasing data, related to a physical characteristic of the transistor, for changing the physical characteristic of the transistor, the setting biasing data including changing a data type of a target polygon pattern included in the transistor, the target polygon pattern corresponding to a component in the transistor;
performing, in a processor, a design rule check (DRC) process for the layout of the semiconductor device while ignoring the biasing data; and
performing, in the processor, an optical proximity correction (OPC) process for the layout of the semiconductor device based on the biasing data.
2. The method of claim 1 , wherein the performing the DRC process includes:
performing the DRC process for the layout of the semiconductor device based on a first data type of the target polygon pattern, the first data type corresponding to a pre-changed data type before the data type of the target polygon pattern is changed.
3. The method of claim 2 , wherein the performing the OPC process includes:
performing the OPC process for the layout of the semiconductor device based on a second data type of the target polygon pattern, the second data type corresponding to a changed data type after the data type of the target polygon pattern is changed.
4. The method of claim 3 , further comprising:
performing a second DRC process for the layout of the semiconductor device based on the second data type of the target polygon pattern.
5. The method of claim 1 , wherein the changing the data type of the target polygon pattern includes modifying a gate length of the transistor.
6. The method of claim 1 , wherein the changing the data type of the target polygon pattern includes modifying a width of the transistor.
7. The method of claim 1 , wherein the setting biasing data further includes establishing a value that is within at least one of design margins and manufacturing process margins for the semiconductor device.
8. The method of claim 1 , wherein the physical characteristic of the transistor includes at least one of a width of the transistor and a gate length of the transistor.
9. A method of claim 1 designing a semiconductor device, the method comprising:
selecting a transistor included in a layout of the semiconductor device;
setting biasing data, related to a physical characteristic of the transistor, for changing the physical characteristic of the transistor, wherein the setting biasing data includes adding a first polygon pattern associated with a target polygon pattern, the target polygon pattern corresponding to a component in the transistor;
performing, in a processor, a design rule check (DRC) process for the layout of the semiconductor device while ignoring the biasing data; and
performing, in the processor, an optical proximity correction (OPC) process for the layout of the semiconductor device based on the biasing data.
10. The method of claim 9 , wherein the setting biasing data further includes:
setting a data type of the first polygon pattern.
11. The method of claim 9 , wherein the performing the DRC process includes:
performing a first DRC process for the layout of the semiconductor device based on the target polygon pattern.
12. The method of claim 11 , further comprising:
performing a second DRC process for the layout of the semiconductor device based on the first polygon pattern.
13. The method of claim 12 , wherein the second DRC process is a process for checking a data type of the first polygon pattern and a layer data of the first polygon pattern.
14. The method of claim 9 , wherein the performing the OPC process includes:
generating a second polygon pattern by merging the target polygon pattern and the first polygon pattern; and
performing the OPC process for the layout of the semiconductor device based on the second polygon pattern.
15. The method of claim 9 , wherein the setting biasing data includes modifying at least one of a gate length of the transistor and a width of the transistor based on the first polygon pattern.
16. A method of modifying a layout of a semiconductor device, the method comprising:
assigning biasing data, related to a physical characteristic of a transistor, associated with change to the physical characteristic of the transistor in the layout of the semiconductor device, the assigning biasing data including adjusting a first data type of the transistor to a second data type, the second data type corresponding to the change to the physical characteristic of the transistor;
performing, in a processor, a design rule check (DRC) process for the layout of the semiconductor device without the biasing data; and
performing, in the processor, an optical proximity correction (OPC) process for the layout of the semiconductor device based on the biasing data.
17. The method of claim 16 , wherein the performing the DRC process includes conducting the DRC process based on the first data type.
18. The method of claim 16 , wherein the performing the OPC process includes conducting the OPC process based on the second data type.
19. The method of claim 18 , further comprising:
conducting a second DRC process based on the second data type prior to conducting the OPC process.
20. The method of claim 16 , wherein the physical characteristic of the transistor includes at least one of a width of the transistor and a gate length of the transistor.