IP Library Granted Patent US 8,625,646
Granted Patent B2
US 8,625,646 · App. 13/012,840 · Granted Jan 7, 2014

Semiconductor device

Inventors: Harumi Nishiguchi (Tokyo, JP); Misao Hironaka (Tokyo, JP); Kyosuke Kuramoto (Tokyo, JP); Masatsugu Kusunoki (Tokyo, JP); Yosuke Suzuki (Tokyo, JP)
Assignee: Mitsubishi Electric Corporation
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Quick Facts
Patent No.
US 8,625,646
App. No.
13/012,840
Granted
Jan 7, 2014
Kind
B2
Abstract

A semiconductor device includes a submount; a semiconductor laser mounted on the submount via solder in a junction-down manner. The semiconductor laser includes a semiconductor substrate, a semiconductor laminated structure containing a p-n junction, on the semiconductor substrate, and an electrode on the semiconductor laminated structure and joined to the submount via the solder. A high-melting-point metal or dielectric film is located between the submount and the semiconductor laminated structure and surrounds the electrode.

Claims (12)

1. A semiconductor device comprising:

a semiconductor laser including

a semiconductor substrate,

a semiconductor laminated structure having opposed first and second surfaces, and containing a p-n junction, wherein the first surface of the semiconductor laminated structure is disposed on the semiconductor substrate,

an electrode disposed on and covering only part of the second surface of the semiconductor laminated structure, and

a high-melting-point metal film disposed on and in direct contact with part of the second surface of the semiconductor laminated structure, and surrounding and disposed on a peripheral part of the electrode, wherein the high-melting-point metal film is chosen from the group consisting of platinum, nickel, nickel-chromium alloy, tungsten, titanium, tungsten-titanium alloy, molybdenum, tantalum, and niobium; and

a submount, wherein the semiconductor laser is mounted on the submount via solder, in a junction-down manner, with the solder interposed between the submount and the electrode, and between the high-melting-point metal film and the submount, with the high-melting-point metal film surrounding the electrode, whereby the high-melting-point metal film prevents the solder from short circuiting the p-n junction.

2. The semiconductor device according to claim 1 , wherein

the semiconductor laminated structure has a channel surrounding the electrode,

an inside surface of the channel is coated with the high-melting-point metal or dielectric film, and

the high-melting-point metal film is not ohmically joined to the semiconductor laminated structure.

3. The semiconductor device according to claim 1 , wherein the solder is chosen from the group consisting of solders that form Au—Sn-based alloys, Sn—Ag-based alloys, Sn—Ag—Cu-based alloys, Sn—Zn-based alloys, Sn—Bi-based alloys, Pb—Sn-based alloys, Au—Si-based alloys, and Au═Ge-based alloys.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 19, 2011
From: NISHIGUCHI, HARUMI; HIRONAKA, MISAO; KURAMOTO, KYOSUKE; KUSUNOKI, MASATSUGU; SUZUKI, YOSUKE
To: MITSUBISHI ELECTRIC CORPORATION
Reel/Frame 026149/0457 →
Priority Claims (1)
JP 2010-088912 · Apr 7, 2010 · national
Continuity (1)
Related Publication 20110249694A1 · Oct 13, 2011