Context state management for processor feature sets
Embodiments of an invention related to context state management based on processor features are disclosed. In one embodiment, a processor includes instruction logic and state management logic. The instruction logic is to receive a state management instruction having a parameter to identify a subset of the features supported by the processor. The state management logic is to perform a state management operation specified by the state management instruction.
1. A processor comprising:
instruction logic to receive a first state management instruction, a second state management instruction, and a third state management instruction, the first state management instruction having a parameter to program a bit vector to identify a subset of a plurality of features supported by the processor, the second state management instruction to read the bit vector, and the third state management instruction to specify a state management operation; and
state management logic to perform the state management operation specified by the third state management instruction for the subset of the plurality of features.
2. The processor of claim 1 , wherein the parameter indicates the features that are enabled.
3. The processor of claim 1 , wherein the parameter indicates the features that are selected for state management.
4. The processor of claim 1 , wherein the state management operation is to save a context.
5. The processor of claim 4 , wherein the state management operation is to save only in-use state.
6. The processor of claim 4 , wherein the state management operation is to save only modified state.
7. The processor of claim 1 , wherein the state management operation is to restore a context.
8. The processor of claim 7 , wherein the state management operation is to restore only valid state.
9. A method comprising:
receiving, by a processor, a first state management instruction having a parameter to program a bit vector to identify a subset of a plurality of features supported by the processor;
receiving, by the processor, a second state management instruction to read the bit vector;
receiving, by the processor, a third state management instruction to specify a state management operation; and
performing, by the processor, the state management operation specified by the third state management instruction for the subset of the plurality of features.
10. The method of claim 9 , wherein the state management operation is to save a context.
11. The method of claim 10 , wherein the state management logic is to save only in-use state.
12. The method of claim 10 , wherein the state management logic is to save only modified state.
13. The method of claim 9 , where in the state management operation is to restore a context.
14. The method of claim 13 , wherein the state management operation is to restore only valid state.
15. The method of claim 9 , wherein the parameter indicates the features that are enabled.
16. The method of claim 9 , wherein the parameter indicates the features that are selected for state management.
17. A system comprising:
a memory to store state; and
a processor including:
instruction logic to receive a first state management instruction, a second state management instruction, and a third state management instruction, the first state management instruction having a parameter to program a bit vector to identify a subset of a plurality of features supported by the processor, the second state management instruction to read the bit vector, and the third state management instruction to specify a state management operation, wherein to state management operation is one of a first operation to save state to the memory and a second operation to restore state from the memory; and
state management logic to perform the third state management operation for the subset of the plurality of features.