Nonvolatile semiconductor memory

1. A nonvolatile semiconductor memory comprising:

a semiconductor substrate;

a first semiconductor layer on the semiconductor substrate;

control gates provided in an array form in a first direction in parallel with a surface of the semiconductor substrate and in a second direction perpendicular thereto, the control gates passing through the first semiconductor layer in a third direction perpendicular to the first and second directions;

data recording layers between the first semiconductor layer and the control gates;

two first conductive-type diffusion layers at two ends in the first direction of the first semiconductor layer;

two second conductive-type diffusion layers at two ends in the second direction of the first semiconductor layer;

select gate lines extending in the first direction on the first semiconductor layer; and

word lines extending in the second direction on the select gate lines,

wherein the select gate lines function as select gates shared by select transistors connected between the control gates and the word lines arranged in the first direction,

each of the word lines is commonly connected to the control gates arranged in the second direction,

a first memory cell array comprises the first semiconductor layer, the control gates, and the data recording layers therebetween, and

the first memory cell array has NAND series including memory cells connected in series in the first direction.

2. The memory of claim 1 ,

wherein a writing to a selected memory cell of a selected NAND series of the NAND series is executed by:

setting the two second conductive-type diffusion layers to a floating state,

setting the control gate of the selected memory cell to a potential for the writing, and

providing charges from one of the two first conductive-type diffusion layers to the selected memory cell.

3. The memory of claim 1 ,

wherein a reading to a selected memory cell of a selected NAND series of the NAND series is executed by:

setting control gates of memory cells in two unselected NAND series adjacent to the selected NAND series and the two second conductive-type diffusion layers to a floating state,

setting the control gate of the selected memory cell to a potential for the reading, and

setting control gates of unselected memory cells in the selected NAND series to a potential at which an electric conduction path is generated in the selected NAND series.

4. The memory of claim 3 ,

wherein when the reading is executed repeatedly multiple times, the control gates of all the memory cells in the selected NAND series are set to a potential for erasing a channel inversion layer in the first semiconductor layer after the reading.

5. The memory of claim 1 ,

wherein a reading to a selected memory cell of a selected NAND series of the NAND series is executed by:

setting the two second conductive-type diffusion layers to a floating state,

setting control gates of memory cells in two unselected NAND series adjacent to the selected NAND series to a potential at which no electric conduction path is generated in the two unselected NAND series,

setting the control gate of the selected memory cell to a potential for the reading, and

setting the control gates of the unselected memory cells in the selected NAND series to a potential at which an electric conduction path is generated in the selected NAND series.

6. The memory of claim 5 ,

wherein when the reading is executed repeatedly multiple times, the control gates of all the memory cells in the selected NAND series are set to a potential for erasing a channel inversion layer formed in the first semiconductor layer after the reading.

7. The memory of claim 1 ,

wherein an erasing to the memory cells in the NAND series is executed by:

setting the two first conductive-type diffusion layers to a floating state,

setting the control gates to a potential for the erasing, and

providing charges from at least one of the two second conductive-type diffusion layers to the memory cells in the NAND series.

8. The memory of claim 1 , further comprising blocks arranged in the first and second directions,

wherein each of the blocks includes the control gates, the data recording layers, the select gate lines, and the word lines, and

one of the two first conductive-type diffusion layers or one of the two second conductive-type diffusion layers is shared by two of the blocks adjacent to each other in the first or second direction.

9. The memory of claim 8 ,

wherein each of the blocks includes select transistors provided at ends in the first direction of the NAND series, and

each of the select transistors has a select gate passing through the first semiconductor layer in the third direction.

10. The memory of claim 9 ,

wherein each of the blocks includes select transistors provided at ends in the second direction of the NAND series, and

each of the select transistors has a select gate passing through the first semiconductor layer in the third direction.

11. The memory of claim 10 ,

wherein a read/write buffer is connected to only one of the two first conductive-type diffusion layers provided at one end of blocks in each of odd-numbered columns or even-numbered columns with respect to an end in the first direction of the blocks.

12. The memory of claim 8 ,

wherein each of the blocks includes select transistors provided at ends in the second direction of the NAND series, and

each of the select transistors has a select gate passing through the first semiconductor layer in the third direction.

13. The memory of claim 12 ,

wherein a read/write buffer is connected to only one of the two first conductive-type diffusion layers provided at one end of blocks in each of odd-numbered channels or even-numbered channels with respect to an end in the first direction of the blocks.

14. The memory of claim 1 , further comprising:

a second semiconductor layer between the first semiconductor layer and the select gate lines, the control gates passing through the second semiconductor layer in the third direction;

data recording layers between the second semiconductor layer and one of the control gates;

two first conductive-type diffusion layers at two ends in the first direction of the second semiconductor layer; and

two second conductive-type diffusion layers at two ends in the second direction of the second semiconductor layer,

wherein a second memory cell array comprises the second semiconductor layer, the control gates, and the data recording layers therebetween, and

the second memory cell array has NAND series including memory cells connected in series in the first direction.

15. The memory of claim 14 , further comprising:

a first conductive line independently connected to one of the two first conductive-type diffusion layers in the first semiconductor layer; and

a second conductive line independently connected to one of the two first conductive-type diffusion layers in the second semiconductor layer.

16. The memory of claim 15 ,

wherein one of the two first conductive-type diffusion layers is provided at one end in the first direction of the first and second semiconductor layers,

one end in the first direction of the first and second semiconductor layer has a staircase structure, and

the first and second semiconductor layers comprising the staircase structure have trenches filled with insulating layers.

17. The memory of claim 15 ,

wherein one of the two first conductive-type diffusion layers is provided at one end in the first direction of the first and second semiconductor layers,

one end in the first direction of the first and second semiconductor layer has a curvature structure curved in the third direction, and

the first and second semiconductor layers comprising the curvature structure have trenches filled with insulating layers.

18. The memory of claim 15 , further comprising:

a first contact plug for connecting between the first conductive line and one of the two first conductive-type diffusion layers in the first semiconductor layer; and

a second contact plug for connecting between the second conductive line and one of the two first conductive-type diffusion layers in the second semiconductor layer,

wherein the first and second contact plugs pass through the first and second semiconductor layers in the third direction.

19. The memory of claim 18 ,

wherein one of the two first conductive-type diffusion layers in the first semiconductor layer has a first fringe area connected to the first contact plug,

one of the two first conductive-type diffusion layers in the second semiconductor layer has a second fringe area connected to the second contact plug,

the first and second fringe areas are displaced from each other when seen from the third direction, and

the first and second conductive lines are connected to ends of the first and second contact plugs at the semiconductor substrate side.

20. The memory of claim 14 , further comprising a first conductive line commonly connected to one of the two first conductive-type diffusion layers in the first and second semiconductor layers,

wherein the first conductive line is connected to one of the two first conductive-type diffusion layers in the first semiconductor layer via a first select transistor array,

the second conductive line is connected to one of the two first conductive-type diffusion layers in the second semiconductor layer via a second select transistor array, and

the first and second select transistor arrays have the same structure as the first and second memory cell arrays.