IP Library Granted Patent US 8,645,762
Granted Patent B2
US 8,645,762 · App. 12/963,086 · Granted Feb 4, 2014

Queue freeze on protocol error

Inventor: Greggory D. Donley (San Jose, CA)
Assignee: Advanced Micro Devices, Inc.
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Quick Facts
Patent No.
US 8,645,762
App. No.
12/963,086
Granted
Feb 4, 2014
Kind
B2
Abstract

A method and apparatus for retrieving a state of a processor at a time at which failure is detected. More specifically, the detection of one or more protocol errors results in the halting of operations of one or more system elements, and the retrieving of the state of the processor at the time of the failure.

Claims (26)

1. A method for halting operations of a cache in a processor when a protocol error is detected, the method comprising;

sending a tag request for processing based on information in a request from a processor core;

receiving a response to the tag request;

detecting one or more protocol errors in the response, the one or more protocol errors include a request to allocate modified data or non-modified data; and

halting operation of one or more elements in the cache based on the detection of the one or more protocol errors.

2. The method of claim 1 wherein the one or more elements include at least one of a local queue and a state machine.

3. The method of claim 1 wherein the one or more elements include the request from the processor core.

4. The method of claim 1 wherein the cache is a sub-cache, and the one or more protocol errors include at least one error regarding multiple hits detected in a sub-cache.

5. The method of claim 1 wherein the one or more protocol errors include a request queue overflow indication.

6. The method of claim 1 wherein the tag request includes an address of a requested line of data.

7. A data cache comprising:

a controller configured to receive one or more requests from one or more processor cores, send one or more tag requests based on the one or more requests and receive a response based on the one or more requests, wherein the response includes one or more protocol errors, the one or more protocol errors include a request to allocate modified data or non-modified data; and

a plurality of sub-caches configured to receive the one or more tag requests and in response to the one or more tag requests send a tag response.

8. The data cache of claim 7 wherein the controller is further configured to detect protocol errors in the response and on a condition that protocol errors are detected, generate a protocol error signal to halt operation of elements in the data cache.

9. The data cache of claim 7 wherein the one or more protocol errors include multiple hits detected in a sub-cache.

10. The data cache of claim 7 wherein the one or more protocol errors include a request queue overflow indication.

11. The data cache of claim 7 wherein the tag request includes an address of a requested line of data.

12. A method for retrieving state information when a protocol error is detected with respect to a cache of a processor, the method comprising:

detecting protocol errors in a tag response, the protocol errors include a request to allocate modified data or non-modified data; and

storing state information for one or more elements in the cache responsive to detection of the protocol errors.

13. The method of claim 10 wherein the one or more protocol errors include multiple hits detected in a sub-cache.

14. The method of claim 10 wherein the one or more protocol errors include a request queue overflow indication.

15. The method of claim 12 further comprising:

scanning the cache to preserve the state information for the one or more elements;

analyzing the state information; and

debugging based on the state information.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2010
From: DONLEY, GREGGORY D.
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 025480/0102 →
Continuity (1)
Related Publication 20120151251A1 · Jun 14, 2012