IP Library Granted Patent US 8,653,436
Granted Patent B2
US 8,653,436 · App. 12/641,133 · Granted Feb 18, 2014

CMOS pixel including a transfer gate overlapping the photosensitive region

Inventor: Hisanori Ihara (Hiroshima, JP)
Assignee: OmniVision Technologies, Inc.
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Quick Facts
Patent No.
US 8,653,436
App. No.
12/641,133
Granted
Feb 18, 2014
Kind
B2
Abstract

A pinned photodiode structure with peninsula-shaped transfer gate which decrease the occurrence of a potential barrier between the photodiode and the floating drain, prevents loss of full well capacity (FWC) and decreases occurrences of image lag.

Claims (32)

1. An apparatus comprising:

a photodiode formed in a substrate, the photodiode including a photosensitive area;

a floating drain formed in the substrate; and

a transfer gate positioned on a surface of the substrate between the photodiode and the floating drain, the transfer gate including a protrusion that extends from an edge of the photosensitive area to a part of the photosensitive area having maximum electrical potential, wherein the transfer gate protrusion is on the same plane as the transfer gate.

2. The apparatus of claim 1 wherein the diode is a pinned photodiode.

3. The apparatus of claim 2 wherein the pinned photodiode includes an n-type photodiode and a p+ pinning layer.

4. The apparatus of claim 1 wherein the protrusion projects substantially perpendicular to a main portion of the transfer gate, such that the transfer gate is substantially T-shaped.

5. The apparatus of claim 1 wherein the protrusion is quadrilateral.

6. The apparatus of claim 1 , further comprising a floating drain well adjacent to the floating drain.

7. The apparatus of claim 1 , further comprising an implant layer formed on a side of the substrate opposite the side of the substrate on which the photodiode is formed.

8. The apparatus of claim 7 wherein the substrate is p-doped, the photodiode is n-doped and the implant layer is a p+ implant layer.

9. A process comprising:

forming a photosensitive area of a photodiode in a substrate;

forming a floating drain in the substrate;

forming a transfer gate on a surface of the substrate between the photodiode and the floating drain, the transfer gate including a protrusion that extends from an edge of the photosensitive area to a part of the photosensitive area having maximum electrical potential.

10. The process of claim 9 , further comprising forming a pinned region of the photodiode.

11. The process of claim 10 wherein the pinned photodiode includes an n-type photodiode and a p+ pinning layer.

12. The process of claim 9 wherein the protrusion projects substantially perpendicular to a main portion of the transfer gate, such that the transfer gate is substantially T-shaped.

13. The process of claim 9 wherein the protrusion is quadrilateral.

14. The process of claim 9 , further comprising forming a floating drain well adjacent to the floating drain.

15. The process of claim 9 , further comprising forming an implant layer on a side of the substrate opposite the side of the substrate on which the photodiode is formed.

16. The process of claim 15 wherein the substrate is p-doped, the photodiode is n-doped and the implant layer is a p+ implant layer.

17. A system comprising:

a CMOS image sensor formed in a substrate, wherein the CMOS image sensor has a pixel array including one or more CMOS pixels comprising:

a photodiode formed in the substrate, the photodiode including a photosensitive area;

a floating drain formed in the substrate; and

a transfer gate positioned on a surface of the substrate between the photodiode and the floating drain, the transfer gate including a protrusion that extends from an edge of the photosensitive area to a part of the photosensitive area having maximum electrical potential; and

processing circuitry coupled to the pixel array to process a signal received from the pixel array.

18. The system of claim 17 wherein the protrusion projects substantially perpendicular to a main portion of the transfer gate, such that the transfer gate is substantially T-shaped.

19. The system of claim 17 , further comprising at least one of a signal conditioning circuit, an analog/digital converter and a digital signal processor coupled to the processing circuitry.

20. The system of claim 19 , further comprising a storage unit, a display unit, or both, coupled to the digital signal processor.

21. The system of claim 17 , further comprising at least one optical element coupled to the CMOS image sensor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2010
From: IHARA, HISANORI
To: OMNIVISION TECHNOLOGIES, INC.
Reel/Frame 024017/0235 →
Continuity (2)
Provisional Application 61143721 · Jan 9, 2009
Related Publication 20100176276A1 · Jul 15, 2010