Inductive and capacitive elements for semiconductor technologies with minimum pattern density requirements
The present invention provides a semiconductor device comprising a plurality of layers, the semiconductor device comprising:—a substrate having a first major surface,—an inductive element fabricated on the first major surface of the substrate, the inductive element comprising at least one conductive line, and—a plurality of tilling structures in at least one layer, wherein the plurality of tilling structures are electrically connected together and are arranged in a geometrical pattern so as to substantially inhibit an inducement of an image current in the tilling structures by a current in the inductive element. It is an advantage of the above semiconductor device that, by using such tilling structures, an inductive element with improved quality factor is obtained. The present invention also provides a method for providing an inductive element in a semiconductor device comprising a plurality of layers.
1. A semiconductor device comprising a plurality of layers, the semiconductor device comprising:
a substrate having a first major surface,
an inductive element fabricated on the first major surface of the substrate of the inductive element comprising at least one conductive line,
a plurality of tilling structures in at least one layer, the plurality of tilling structures arranged to improve manufacturability of the semiconductor device,
wherein the plurality of tilling structures are electrically connected together and arranged in a geometrical pattern so as to substantially inhibit an inducement of an image current in the tilling structures by a current in the inductive element, and, wherein the geometrical pattern of tilling structures does not substantially inhibit inductive coupling between the inductive element and the substrate, and wherein the tilling structures are connected to a DC potential.
2. A semiconductor device according to claim 1 , the tilling structures being made from tilling structure material, wherein the plurality of tilling structures are arranged in a pattern so that the amount of tilling structure material in an area closer to the inductive element is smaller than the amount of tilling structure material in an area farther away from the inductive element.
3. A semiconductor device according to claim 1 , wherein the and wherein the arrangement of the tilling structures is determined by a desired pattern density of the semiconductor device for improving at least one of a process window of lithography, uniformity of chemical mechanical polishing removal rate and integrity of low-k dielectrics.
4. A semiconductor device according to claim 3 , wherein the geometrical pattern of tilling structures at two different layers is different in shape and/or orientation.
5. A semiconductor device according to claim 3 , wherein the tilling structures at different layers are electrically connected to each other.
6. A semiconductor device according to claim 1 , wherein the tilling structures are a plurality of substantially triangular elements.
7. A semiconductor device according to claim 6 , wherein the elements of the tilling structures are locally oriented perpendicular to the at least one conductive line of the inductive element.
8. A semiconductor device according to claim 1 , furthermore comprising a ground shield for shielding the inductive element from a further layer.
9. A semiconductor device according to claim 8 , wherein the further layer is the substrate.
10. A semiconductor device according to claim 8 , furthermore comprising connection means electrically connecting the plurality of tilling structures with the ground shield without creating a conductive loop.
11. A semiconductor device according to claim 1 , wherein the tilling structures are formed in a region other than a region directly below the inductive element.
12. A semiconductor device according to claim 1 , furthermore provided with a further passive element.
13. A semiconductor device according to claim 12 , wherein the further passive element is a capacitive element.
14. A semiconductor device according to claim 13 , wherein the capacitive element comprises two capacitor electrodes at least one of the capacitor electrodes being formed by a plurality of tilling structures.
15. A semiconductor device according to claim 13 , wherein the integration of the capacitive element with the inductive element is optimized to respect the metal pattern density in advanced silicon technologies.
16. A semiconductor device according to claim 13 , wherein the distance between the capacitive element and the inductive element is large enough to avoid a dominant fringe coupling between them.
17. A semiconductor device according to claim 14 , wherein a capacitor electrode formed by a plurality of tilling structures leads to a metal or polysilicon or active region density in the inductor vicinity respecting the design rules of advanced IC technologies.
18. A semiconductor device according to claim 14 , wherein one capacitor electrode of the capacitive element is formed by a ground shield.
19. A semiconductor device comprising a plurality of layers, the semiconductor device comprising:
a substrate having a first major surface,
an inductive element fabricated on the first major surface of the substrate of the inductive element comprising at least one conductive line,
a plurality of tilling structures in at least one layer, the plurality of tilling structures arranged to improve manufacturability of the semiconductor device,
wherein the plurality of tilling structures are electrically connected together and arranged in a geometrical pattern so as to substantially inhibit an inducement of an image current in the tilling structures by a current in the inductive element, and, wherein the geometrical pattern of tilling structures does not substantially block penetration into the substrate of electric field lines generated by the inductive element, and wherein the tilling structures are a plurality of slender elongate elements.
20. A semiconductor device according to claim 19 , wherein the elements of the tilling structures are locally oriented perpendicular to the at least one conductive line of the inductive element.