Depth-optimal mapping of logic chains in reconfigurable fabrics
View Patent ↗A method of creating logic chains in a Boolean network of a reconfigurable fabric is provided. The method includes creating a plurality of logic chains in the reconfigurable fabric. The plurality of logic chains include at least one arithmetic logic chain and at least one non-arithmetic logic chain. A method of creating logic chains in a Boolean network of a look-up table based FPGA includes: applying a labeling method by (a) finding a depth increasing node, (b) isolating the depth increasing node, and (c) finding minimum height cuts; mapping to generate a mapping solution using the minimum height cuts; applying a duplication method to implement an exclusivity constraint; and arranging connections in the look-up table based FPGA using the logic chains.
1. A method of creating logic chains in a Boolean network representing a logic circuit and mapping the logic circuit to an electronic circuit, the method comprising:
creating a plurality of generic logic chains in the logic circuit with each of the generic logic chains being useable for arithmetic operations or non-arithmetic operations; and
mapping the plurality of logic chains in the logic circuit to an electronic circuit;
wherein each of the logic chains being a subnetwork of adjacent nodes with equal routing depth and increasing logic depth.
2. The method of claim 1 , wherein each of the plurality of logic chains being created in polynomial time.
3. The method of claim 1 wherein each of the plurality of logic chains being created without HDL arithmetic chain macros.
4. The method of claim 1 wherein the creating the plurality of logic chains comprises labeling.
5. The method of claim 4 wherein the labeling further comprises finding a depth increasing node.
6. The method of claim 5 wherein the labeling further comprises isolating the depth increasing node.
7. The method of claim 6 wherein the labeling further comprises finding minimum height cuts.
8. The method of claim 7 wherein the creating the plurality of logic chains further comprises mapping to generate a mapping solution using the minimum height cuts.
9. The method of claim 8 wherein the creating the plurality of logic chains further comprises applying a duplication method to implement an exclusivity constraint.
10. The method of claim 9 wherein the creating the plurality of logic chains further comprises applying a relaxation method to relax routing depth.
11. The method of claim 10 wherein the relaxation method comprises a least critical branch trimming method.
12. The method of claim 1 wherein the reconfigurable fabric is a field programmable gate array (FPGA).
13. A process of creating logic chains in a Boolean network representing a logic circuit, the logic circuit suitable for mapping to an electronic circuit, the process comprising:
creating a plurality of generic logic chains with each of the generic logic chains being useable for arithmetic operations or non-arithmetic operations; and
wherein each of the logic chains being a sub network of adjacent nodes with equal routing depth and increasing logic depth of the logic circuit.
14. The process of claim 13 further comprising mapping the logic circuit to the electronic circuit.
15. A method of creating logic chains in a Boolean network representing a logic circuit, the logic circuit suitable for mapping to an electronic circuit, the process comprising:
creating a plurality of generic logic chains from adjacent cell interconnection structures with each of the generic logic chains being useable for arithmetic operations or non-arithmetic operations;
wherein each of the logic chains being a sub network of adjacent nodes with equal routing depth and increasing logic depth of the logic circuit.
16. The method of claim 15 wherein each of the plurality of generic logic chains is associated with a depth increasing node in the logic circuit.
17. The method of claim 15 wherein the mapping is performed without preserving hardware description language (HDL) macros.