A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area and forming first and second gates of first and second transistors in the cell area. The first gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the first gate are separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. The method also includes forming first and second junctions of the first and second transistors. A first gate terminal is formed and coupled to the second sub-gate of the first transistor. A second gate terminal is formed and coupled to at least the first sub-gate of the second transistor.
1. A device comprising:
a cell having first and second transistors coupled in series, wherein the first and second transistors are disposed between first and second cell terminals, wherein
the first transistor includes a first gate with a second sub-gate surrounding a first sub-gate, the first and second sub-gates of the first gate are separated by a first intergate dielectric layer, and
the second transistor includes a second gate with a second sub-gate surrounding a first sub-gate, the first and second sub-gates of the second gate are separated by a second intergate dielectric layer;
a first gate terminal coupled to the second sub-gate of the first gate; and
a second gate terminal coupled to at least the first sub-gate of the second gate.
2. The device of claim 1 wherein:
the first transistor serves as a control gate;
the second transistor serves as a select gate;
the first cell terminal is coupled to a first junction of the first transistor and serves as a bitline; and
the second gate terminal serves as a wordline.
3. The device of claim 1 wherein the first intergate dielectric layer comprises multiple dielectric layers.
4. The device of claim 1 wherein the second gate terminal is coupled to the first and second sub-gates of the second gate.
5. The device of claim 1 wherein the second gate terminal is coupled to the first sub-gate of the second gate while the second sub-gate of the second gate is floated.
6. A device comprising:
a cell having first and second transistors coupled in series, wherein
the first transistor includes a first gate with a second sub-gate surrounding a first sub-gate, the first and second sub-gates of the first gate are separated by a first intergate dielectric layer, and
the second transistor includes a second gate with a second sub-gate surrounding a first sub-gate, the first and second sub-gates of the second gate are separated by a second intergate dielectric layer;
a first gate terminal coupled to the second sub-gate of the first gate; and
a second gate terminal coupled to at least the first sub-gate of the second gate.
7. The device of claim 6 wherein the second gate terminal is coupled to the first and second sub-gates of the second gate.
8. The device of claim 6 wherein the second gate terminal is coupled to the first sub-gate of the second gate while the second sub-gate of the second gate is floated.
9. The device of claim 6 wherein:
the first and second transistors are disposed between first and second cell terminals; and
the first and second transistors comprise first and second doped regions adjacent to the first and second gates.
10. The device of claim 9 wherein the first and second doped regions comprise first and second sub-portions, wherein the second sub-portions are encompassed within the first sub-portions.
11. The device of claim 9 wherein the first and second doped regions of the first and second transistors include a heavily doped portion and a lightly doped extension portion extending from the first gate to the second gate.
12. The device of claim 9 wherein:
the first cell terminal is coupled to the first doped region of the first transistor; and
the second cell terminal is coupled to the first doped region of the second transistor.
13. The device of claim 12 wherein:
the first cell terminal serves as a bitline; and
the second gate terminal serves as a wordline.
14. The device of claim 9 wherein the second doped regions of the first and second transistors are a common second doped region.
15. The device of claim 6 wherein:
the first transistor serves as a control gate; and
the second transistor serves as a select gate.
16. The device of claim 6 wherein the first intergate dielectric layer comprises multiple dielectric layers.
17. The device of claim 16 wherein the first intergate dielectric layer comprises an oxide-nitride-oxide stack.
18. The device of claim 6 wherein the device comprises an ETOX device.
19. A device comprising:
a cell having first and second transistors coupled in series, wherein
the first transistor includes a first gate with a second sub-gate surrounding a first sub-gate, the first and second sub-gates of the first gate are separated by a first intergate dielectric layer, and
the second transistor includes a second gate with a second sub-gate surrounding a first sub-gate, the first and second sub-gates of the second gate are separated by a second intergate dielectric layer; and
a first gate terminal coupled to at least the first sub-gate of the first gate.
20. The device of claim 19 comprising a second gate terminal coupled to the second sub-gate of the second gate.