Common mode termination with C-multiplier circuit
Embodiments of the present disclosure provide input termination circuits that overcome the deficiencies of conventional designs. Specifically, embodiments eliminate large-on chip bypass capacitors that are commonly used for common mode termination, and instead use an active capacitor-multiplier (C-multiplier) circuit at the common mode node. The C-multiplier circuit mimics a large capacitor at high frequency. By eliminating large on-chip bypass capacitors, the IC design (e.g., receiver) is reduced in size, without affecting common mode return loss performance. Embodiments may be used with any applications that require input termination, and particularly with differential applications that require common mode termination.
1. An input termination circuit having first and second input terminals, comprising:
a first resistive element having a first end coupled to the first input terminal and a second end coupled to a common mode node of the input termination circuit;
a second resistive element having a first end coupled to the second input terminal and a second end coupled to the common mode node; and
a capacitor-multiplier circuit, coupled to the common mode node, comprising:
a capacitor having first end and a second end, the first end coupled to the common mode node; and
a transconductance stage coupled between the second end of the capacitor and a ground terminal.
2. The input termination circuit of claim 1 , wherein the capacitor-multiplier circuit is configured to set to zero or near zero an alternating current (AC) voltage at the common mode node.
3. The input termination circuit of claim 2 , wherein the transconductance stage includes a diode-connected transistor.
4. The input termination circuit of claim 2 , wherein the transconductance stage includes an NMOS transistor and an amplifier coupled between a drain terminal and a gate terminal of the NMOS transistor.
5. The input termination circuit of claim 4 , wherein the amplifier is configured to reduce an input resistance of the input termination circuit.
6. The input termination circuit of claim 2 , wherein the capacitor-multiplier circuit further comprises:
a first current source coupled between the common mode node and the ground terminal.
7. The input termination circuit of claim 6 , wherein the first current source comprises a NMOS cascode stage.
8. The input termination circuit of claim 6 , wherein the transconductance stage and the first current source form a current mirror circuit.
9. The input termination circuit of claim 8 , wherein the transconductance stage is configured to sink a first AC current, wherein the first AC current is equivalent to an AC current that flows through the capacitor.
10. The input termination circuit of claim 9 , wherein the first current source is configured to sink a second AC current, wherein the second AC current is equivalent to an integer multiple of the first AC current.
11. The input termination circuit of claim 6 , wherein the capacitor-multiplier circuit further comprises:
a second current source coupled between a supply voltage terminal and the first end of the capacitor; and
a third current source coupled between the supply voltage terminal and the second end of the capacitor.
12. The input termination circuit of claim 2 , wherein the capacitor-multiplier circuit comprises:
a PMOS stage coupled to the capacitor; and
a NMOS stage coupled to the capacitor.
13. The input termination circuit of claim 12 , wherein the PMOS stage is configured to sink zero or near zero AC current.
14. The input termination circuit of claim 12 , wherein the NMOS stage is configured to sink a first AC current, wherein the first AC current is substantially equal to a multiple of an AC current that flows through the capacitor.
15. A device, comprising:
a first circuit;
a second circuit; and
an input termination circuit, coupled between the first circuit and the second circuit, wherein the input termination circuit comprises:
a first resistive element having a first end coupled to a first input terminal of the input termination circuit and a second end coupled to a common mode node of the input termination circuit;
a second resistive element having a first end coupled to a second input terminal of the input termination circuit and a second end coupled to the common mode node; and
a capacitor-multiplier circuit coupled to the common mode node, wherein the capacitor-multiplier circuit comprises:
a capacitor having a first end and a second end, the first end coupled to the common mode node; and
a transconductance stage coupled between the second end of the capacitor and a ground terminal.
16. The device of claim 15 , wherein the capacitor-multiplier circuit is configured to set to zero or near zero an alternating current (AC) voltage at the common mode node of the input termination circuit.
17. The device of claim 15 , wherein the first input terminal and the second input terminal of the input termination circuit are configured to receive a differential input signal from the first circuit.
18. The device of claim 17 , wherein the input termination circuit is configured to terminate a common mode signal of the differential input signal.
19. The device of claim 17 , wherein the input termination circuit is configured to provide differential impedance matching between the first circuit and the second circuit.
20. The device of claim 15 , wherein the second circuit includes one of a wireless antenna and an optical transceiver, and wherein the first circuit includes one of a radio frequency (RF) receiver and serializer-deserializer (SERDES) module.