Asymmetric slotted waveguide and method for fabricating the same
An asymmetric slotted waveguide and method for fabricating the same. The slotted waveguide is constructed in silicon-on-insulator using a Complementary metal-oxide-semiconductor (CMOS) process. One or more wafers can be coated with a photo resist material using a photolithographic process in order to thereby bake the wafers via a post apply bake (PAB) process. An anti-reflective coating (TARC) can be further applied on the wafers and the wafers can be exposed on a scanner for the illumination conditions. After a post exposure bake (PEB), the wafers can be developed in a developer using a puddle develop process. Finally, the printed wafers can be processed using a shrink process to reduce the critical dimension (CD) of the slot and thereby achieve an enhanced asymmetric slotted waveguide that is capable of guiding the optical radiation in a wide range of optical modulation applications using an electro-optic polymer cladding.
1. A method for fabricating an asymmetric slotted waveguide, said method comprising:
coating at least one wafer with a photo resist material using a photolithographic process in order to thereby bake said at least one wafer via a post apply bake process;
applying an anti-reflective coating on said at least one wafer by exposing said at least one wafer on a scanner for the illumination conditions in order to thereby develop said at least one wafer in a developer using a puddle develop process; and
processing said at least one wafer using a shrink process to reduce a critical dimension (CD) of said wafer and to thereby achieve an enhanced asymmetric slotted waveguide that is capable of guiding optical radiation in a wide range of optical modulation applications using an electro-optic polymer cladding.
2. The method of claim 1 further comprising constructing said slotted waveguide in a silicon-on-insulator using a Complementary metal-oxide-semiconductor process.
3. The method of claim 1 further comprising:
adapting a standard photolithographic process to coat said photo resist material on said at least one wafer; and
performing a shrinking process to shrink said critical dimension of features of said at least one wafer.
4. The method of claim 1 further comprising removing said anti-reflective coating from said at least one wafer during said puddle develop process.
5. The method of claim 1 further comprising employing said asymmetric slotted waveguide for the suppression of a second order TE optical mode and TE1 optical mode.
6. The method of claim 1 comprising achieving enhanced coupling with a curved coupler with said asymmetric slotted waveguide.
7. The method of claim 1 wherein said developer comprises a AZ 300 MIF developer.
8. The method of claim 1 wherein said puddle develop process comprises a single 60 s puddle develop process.
9. The method of claim 1 wherein said anti-reflective coating can be an AZ Electronics Aquatar VII at a thickness of 430 A.
10. A product of a method for fabricating an asymmetric slotted waveguide, said method comprising:
coating at least one wafer with a photo resist material using a photolithographic process in order to thereby bake said at least one wafer via a post apply bake process;
applying an anti-reflective coating on said at least one wafer by exposing said at least one wafer on a scanner for the illumination conditions in order to thereby develop said at least one wafer in a developer using a puddle develop process; and
processing said at least one wafer using a shrink process to reduce a critical dimension (CD) of said wafer and to thereby achieve an enhanced asymmetric slotted waveguide that is capable of guiding optical radiation in a wide range of optical modulation applications using an electro-optic polymer cladding.
11. The product of the method of claim 10 , wherein the method is further comprising constructing said slotted waveguide in a silicon-on-insulator using a Complementary metal-oxide-semiconductor process.
12. The product of the method of claim 10 , wherein the method is further comprising:
adapting a standard photolithographic process to coat said photo resist material on said at least one wafer; and
performing a shrinking process to shrink said critical dimension of features of said at least one wafer.
13. The product of the method of claim 10 , wherein the method is further comprising removing said anti-reflective coating from said at least one wafer during said puddle develop process.
14. The product of the method of claim 10 , wherein the method is further comprising employing said asymmetric slotted waveguide for the suppression of a second order TE optical mode and TE1 optical mode.
15. The product of the method of claim 10 , wherein the method is further comprising achieving enhanced coupling with a curved coupler with said asymmetric slotted waveguide.
16. The product of the method of claim 10 wherein said developer comprises a AZ 300 MIF developer.
17. The product of the method of claim 10 wherein said puddle develop process comprises a single 60 s puddle develop process.
18. The product of the method of claim 10 wherein said anti-reflective coating can be an AZ Electronics Aquatar VII at a thickness of 430 A.