Granted Patent B2

US 8,669,124 · App. 13/059,410 · Granted Mar 11, 2014

Inventor: Matthias Merz (Leuven, BE)

Assignee: NXP, B.V.

Abstract

Claims (37)

1. A method of fabricating a detector device, comprising:

forming a source region, a drain region and a gate contact on a substrate, with a channel region between the source and drain regions;

forming an insulator layer over the substrate;

forming first vias through the insulator layer and filling the vias with conductor material, wherein the first vias are provided over the source, drain regions and gate contact,

wherein the method further comprises:

forming an additional via through the insulator layer over a gate channel region which is on top of the channel region, and filling the additional via with said conductor material;

removing the conductor material filling from the additional via to form a first chamber leading to a first side of the gate channel region,

and wherein the method further comprises etching a nanopore from the first chamber through the channel region.

2. A method as claimed in claim 1 , wherein the nanopore is etched through to the opposite side of the substrate.

3. A method as claimed in claim 2 , further comprising locally thinning the substrate at the gate channel region to form a second chamber opposite the first chamber.

4. A method as claimed in claim 1 , further comprising:

forming fluid chambers on opposite sides of the nanopore and filling them with electrolyte;

connecting drive means to the fluid chambers;

connecting drive means to the source and drain regions and gate contact; and

providing a current sensor for sensing a charge flow between the source and drain regions.

5. A method as claimed in claim 1 , further comprising forming a dielectric liner in the first chamber before etching the nanopore.

6. A method as claimed in claim 5 , further comprising etching the dielectric liner to remove a portion of the dielectric liner at the location where the nanopore is to be formed.

7. A method as claimed in claim 1 , wherein the nanopore is formed by a wet etch process.

8. A method as claimed in claim 7 , wherein the wet etch process comprises electrochemical etching.

9. A method as claimed in claim 1 , wherein the nanopore is formed by particle trace etching.

10. A method as claimed in claim 1 , wherein forming an insulator layer comprises forming a stack of insulator layers and conductor layers, thereby providing multiple isolated conductor layers.

11. A detector device, comprising:

a substrate;

a source region, a drain region and a gate contact on the substrate;

a channel region between the source and drain regions;

a gate on top of the channel region;

an insulator layer over the substrate;

first vias through the insulator layer filled with conductor material, wherein the first vias are provided over the source and drain region and gate contact,

an additional via through the insulator layer over the gate, the additional via defining a chamber leading to a first side of the gate channel region,

a nanopore which passes through the channel region, and which connects fluid chambers on opposite sides of the nanopore;

a driver for providing a voltage bias between the fluid chambers;

a driver for providing a voltage between the source and drain regions and gate; and

a current sensor for sensing a charge flow between the source and drain regions.

12. A device as claimed in claim 11 , wherein the nanopore passes through the substrate.

13. A device as claimed in claim 11 , wherein the substrate has a locally thinner region in the vicinity of the nanopore.

14. A device as claimed in claim 13 , wherein the locally thinner region has a thickness of less than 200 nm.

15. A device as claimed in claim 11 , wherein the nanopore has a diameter of less than 10 nm.

Assignments (10)

Priority Claims (1)

Continuity (1)