Array substrate and manufacturing method thereof
A manufacturing method of an array substrate includes the following steps. A first conductive layer, a gate insulating layer, a semiconductor layer, an etching stop layer, and a first patterned photoresist are successively formed on a substrate. The etching stop layer and the semiconductor layer uncovered by the first patterned photoresist are then removed by a first etching process. A patterned gate insulating layer and a patterned etching stop layer are then formed through a second etching process. The first conductive layer uncovered by the patterned gate insulating layer is then removed to form a gate electrode. The semiconductor layer uncovered by the patterned etching stop layer is then removed to form a patterned semiconductor layer and partially expose the patterned gate insulating layer.
1. An array substrate, comprising:
a substrate; and
a thin film transistor, disposed on the substrate, wherein the thin film transistor comprises:
a gate electrode, disposed on the substrate;
a patterned gate insulating layer, disposed on the gate electrode;
a patterned semiconductor layer, disposed on the patterned gate insulating layer;
a patterned etching stop layer, disposed on the patterned semiconductor layer;
a protective layer, disposed on the patterned etching stop layer, wherein the protective layer and the patterned etching stop layer have a plurality of contact openings that partially expose the patterned semiconductor layer; and
a source electrode and a drain electrode, disposed on the protective layer and the patterned semiconductor layer, and the source electrode and the drain electrode are electrically connected to the patterned semiconductor layer via the contact openings.
2. The array substrate of claim 1 , further comprising a pad electrode disposed on the substrate, wherein the pad electrode is not covered by the protective layer.
3. The array substrate of claim 1 , further comprising an isolation layer, disposed on the substrate, wherein the isolation layer at least partially covers the source electrode, the drain electrode and the protective layer.
4. The array substrate of claim 3 , wherein the isolation layer has an opening, and the opening at least partially exposes the thin film transistor.
5. The array substrate of claim 3 , further comprising a pixel electrode, disposed on the drain electrode, wherein the pixel electrode at least partially overlaps the patterned semiconductor layer along a direction perpendicular to the substrate, and the isolation layer has a pixel opening to at least partially expose the pixel electrode.
6. The array substrate of claim 3 , further comprising a pixel electrode disposed between the drain electrode and the protective layer, wherein the pixel electrode at least partially overlaps the patterned semiconductor layer along a direction perpendicular to the substrate, and the isolation layer has a pixel opening that at least partially expose the pixel electrode.
7. The array substrate of claim 3 , further comprising a pixel electrode, at least partially disposed between the substrate and the drain electrode, wherein the isolation layer has a pixel opening to at least partially expose the pixel electrode.
8. The array substrate of claim 3 , wherein the isolation layer comprises a vertically stacked structure, an upper layer of the vertically stacked structure is organic material, and a lower layer of the vertically stacked structure is inorganic material, wherein the inorganic material comprises indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO), indium gallium tin oxide (IGTO), aluminum zinc oxide (AZO), antimony tin oxide (ATO), gallium zinc oxide (GZO), or indium gallium zinc oxide (IGZO).
9. The array substrate of claim 1 , wherein the patterned semiconductor layer comprises an oxide semiconductor material, an amorphous silicon semiconductor material, or a poly silicon semiconductor material.