Reset pulse encoding and decoding scheme with no internal clock
An integrated circuit (IC) provides a reset function. The IC receives a command that is defined by a first sequence of counts of signal transitions of a first signal during windows of a second signal and provides a reset function when it is determined that the command is received. A device including the IC and a system including the device are provided.
1. An integrated circuit (IC) comprising:
circuitry for receiving a command that is defined by a first sequence of counts of signal transitions of a first signal during windows of a second signal; and
circuitry for effecting a function when it is determined that the command is received,
wherein the second signal comprises a pulse train having a plurality of decreasing duration windows separated by constant spaces, and wherein the first signal comprises a decreasing number of counts corresponding to each decreasing duration window of the second signal.
2. An IC according to claim 1 , wherein the circuitry for effecting a function comprises circuitry for effecting a reset function.
3. An IC according to claim 2 , wherein the circuitry for effecting a reset function comprises a circuitry for generating a reset signal.
4. An IC according to claim 1 , wherein the first signal and the second signal comprise one of:
the windows in the second signal are of different periods and the transitions of the first signal are at regular intervals; and
the windows in the second signal have the same period and the transitions of the first signal are at different intervals.
5. An IC according to claim 1 , wherein at least one of the first signal and the second signal is received over a signal path external to the IC.
6. An IC according to claim 5 , wherein the IC has no external reset input.
7. An IC according to claim 1 , further comprising:
circuitry for determining that the command is received at least twice consecutively; and
circuitry for defining the command by a second sequence of counts that is different than the first sequence of counts when it is determined that the command is received at least twice consecutively.
8. An IC according to claim 7 , wherein the second sequence of counts is hardcoded in the IC or received as part of the first signal or second signal during operation.
9. An IC according to claim 1 , wherein the circuitry for effecting a function when it is determined that the command is received comprises circuitry for effecting a function when it is determined that the command is received and an identity of the IC matches an identity information that is included in at least one of the first and second signals.
10. A device comprising:
circuitry for receiving a command that is defined by a first sequence of counts of signal transitions of a first signal during windows of a second signal; and
circuitry for effecting a function when it is determined that the command is received,
wherein the second signal comprises a pulse train having a plurality of decreasing duration windows separated by constant spaces, and wherein the first signal comprises a decreasing number of counts corresponding to each decreasing duration window of the second signal.
11. A device according to claim 10 , further comprising:
circuitry for determining if the command is received at least twice consecutively; and
circuitry for defining the command by a second sequence of counts that is different than the first sequence of counts when it is determined that the command is received at least twice consecutively.
12. A device according to claim 10 , wherein the device comprises an imaging device.
13. A system comprising:
a device comprising:
circuitry for receiving a command that is defined by a first sequence of counts of signal transitions of a first signal during windows of a second signal;
circuitry for effecting a function when it is determined that the command is received comprising circuitry for effecting a reset function;
circuitry for determining that the command is received at least twice consecutively;
circuitry for changing the first sequence of counts to a second sequence of counts that is different than the first sequence when it is determined that the command is received at least twice consecutively; and
a controller coupled to the device that sends at least part of the command to the device,
wherein the controller comprises:
circuitry for determining that the device is not effecting the reset function after receiving the command from the controller; and
circuitry for sending the command to the device at least twice consecutively when the controller determines that the device is not effecting the reset function; and
wherein the device further comprises:
circuitry for defining the command by a second sequence of counts that is different than the first sequence of counts when it is determined that the command is received at least twice consecutively.
14. A method comprising:
receiving a command that is defined by a first sequence of counts of signal transitions of a first signal during windows of a second signal; and
effecting a function when it is determined that the command is received,
wherein the second signal comprises a pulse train having a plurality of decreasing duration windows separated by constant spaces, and wherein the first signal comprises a decreasing number of counts corresponding to each decreasing duration window of the second signal.
15. A method according to claim 14 , wherein effecting a function comprises effecting a reset function.
16. A method according to claim 14 , further comprising determining if the command is received at least twice consecutively; and
defining the command by a second sequence of counts that is different than the first sequence of counts when it is determined that the command is received at least twice consecutively.