Method of integrating a charge-trapping gate stack into a CMOS flow
Embodiments of a method of integration of a non-volatile memory device into a MOS flow are described. Generally, the method includes: forming a dielectric stack on a surface of a substrate, the dielectric stack including a tunneling dielectric overlying the surface of the substrate and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack; patterning the cap layer and the dielectric stack to form a gate stack of a memory device in a first region of the substrate and to remove the cap layer and the charge-trapping layer from a second region of the substrate; and performing an oxidation process to form a gate oxide of a MOS device overlying the surface of the substrate in the second region while simultaneously oxidizing the cap layer to form a blocking oxide overlying the charge-trapping layer. Other embodiments are also disclosed.
1. A method comprising:
forming a dielectric stack on a surface of a substrate, the dielectric stack including a tunneling dielectric overlying the surface of the substrate and a charge-trapping layer overlying the tunneling dielectric;
forming a cap layer overlying the dielectric stack, wherein the cap layer comprises a multi-layer cap layer including at least a first cap layer overlying the charge-trapping layer, and a second cap layer overlying the first cap layer;
patterning the cap layer and the dielectric stack to form a gate stack of a memory device in a first region of the substrate and to remove the cap layer and the charge-trapping layer from a second region of the substrate;
removing the second cap layer; and
performing an oxidation process to form a gate oxide of a metal-oxide-semiconductor (MOS) device overlying the surface of the substrate in the second region while simultaneously oxidizing the cap layer to form a blocking oxide overlying the charge-trapping layer, wherein the oxidation process consumes substantially all of the first cap layer.
2. The method of claim 1 , wherein the first cap layer and the second cap layer comprise silicon nitride or silicon oxynitride.
3. The method of claim 2 , wherein the second cap layer comprises a stoichiometry different from the first cap layer.
4. The method of claim 1 , further comprising removing the tunneling dielectric and a pad oxide overlying the surface of the substrate in the second region prior to performing the oxidation process.
5. The method of claim 4 , further comprising forming a sacrificial oxide over the second cap layer, and wherein removing the second cap layer further comprises removing the sacrificial oxide and the tunneling dielectric.
6. The method of claim 1 , wherein the oxidation process is a radical oxidation process comprising flowing hydrogen (H 2 ) gas and oxygen (O 2 ) gas are flowed into a process chamber in which the substrate is placed to form radicals at a surface of cap layer and the surface of the substrate in the second region.
7. The method of claim 1 , wherein the oxidation process consumes a portion of the charge-trapping layer.
8. The method of claim 7 , wherein the charge-trapping layer comprises a multi-layer charge-trapping layer including at least a first charge-trapping layer closer to the tunneling dielectric, and an second charge-trapping layer that is oxygen-lean relative to the first charge-trapping layer and comprises a majority of a charge traps distributed in multi-layer charge-trapping layer.
9. The method of claim 8 , wherein the multi-layer charge-trapping layer further comprises an oxide layer separating the first charge-trapping layer and the second charge-trapping layer.
10. The method of claim 8 , wherein the second charge-trapping layer comprises a thickness determined by the portion of the charge-trapping layer consumed in the oxidation process.
11. The method of claim 1 , further comprising prior to forming the dielectric stack on the surface of the substrate forming a channel of the memory device in the first region of the substrate and a channel of the MOS device in the second region.
12. The memory device of claim 11 , wherein the channel of the memory device is formed from a semiconducting material overlying the surface of the substrate, and wherein the dielectric stack overlies and abuts the channel of the memory device on at least two sides thereof.
13. A method comprising:
forming a dielectric stack in at least a first region of a substrate, the dielectric stack including a tunneling dielectric overlying a surface of the substrate and a charge-trapping layer overlying the tunneling dielectric;
forming a cap layer overlying the dielectric stack;
forming a sacrificial oxide over the cap layer;
patterning the sacrificial oxide, cap layer and dielectric stack to form a gate stack in the first region of the substrate, and to remove the sacrificial oxide, cap layer and dielectric stack from a second region of the substrate;
removing the sacrificial oxide and a portion of the cap layer from the gate stack while removing the remaining dielectric from the second region; and
performing an oxidation process to form a gate oxide overlying the surface of the substrate in the second region while simultaneously oxidizing the cap layer to form a blocking oxide overlying the charge-trapping layer.
14. The method of claim 13 , wherein the cap layer comprises a multi-layer cap layer including at least a first cap layer overlying the charge-trapping layer, and a second cap layer overlying the first cap layer, and wherein removing a portion of the cap layer comprises removing the second cap layer.
15. The method of claim 14 , wherein the second cap layer comprises a stoichiometry different from the first cap layer.
16. A method comprising:
forming a dielectric stack in at least a first region of a substrate, wherein the dielectric stack includes a tunneling dielectric overlying a surface of the substrate and a charge-trapping layer overlying the tunneling dielectric;
forming a first cap layer overlying the charge-trapping layer, and a second cap layer overlying the first cap layer;
patterning the first and second cap layers and dielectric stack to form a gate stack in the first region of the substrate, and to remove the first and second cap layers and the dielectric stack from a second region of the substrate;
removing the second cap layer from the gate stack in a wet clean process; and
performing an oxidation process to form a gate oxide overlying the surface of the substrate in the second region while simultaneously oxidizing the first cap layer to form a blocking oxide overlying the charge-trapping layer.
17. The method of claim 16 , wherein the second cap layer comprises a stoichiometry different from the first cap layer.
18. The method of claim 16 , further comprising forming a sacrificial oxide over the second cap layer, and wherein patterning the first and second cap layers comprises patterning the sacrificial oxide in the first region of the substrate and removing the sacrificial oxide from the second region of the substrate, and wherein removing the second cap layer from the gate stack in a wet clean process comprises removing the sacrificial oxide.