Semiconductor device having a plurality of repair fuse units
A semiconductor system includes a controller; a semiconductor device comprising a plurality of stacked semiconductor chips stacked over the controller, and a plurality of through-silicon vias (TSVs) configured to commonly transfer a signal to the plurality of stacked semiconductor chips; and a defect information transfer TSV configured to transfer TSV defect information sequentially outputted from at least one of the semiconductor chips to the controller, wherein the controller comprises: a plurality of first repair fuse units configured to set first fuse information based on the TSV defect information; and a plurality of first TSV selection units configured to selectively drive the TSVs in response to the first fuse information.
1. A semiconductor system comprising:
a controller; and
a semiconductor device comprising a plurality of stacked semiconductor chips stacked over the controller, and a plurality of through-silicon vias (TSVs) configured to commonly transfer a signal to the plurality of stacked semiconductor chips,
wherein at least one of the semiconductor chips comprises a plurality of first repair fuse units configured to set first fuse information corresponding to a TSV defect information, and sequentially outputs the TSV defect information, and
the controller comprises a plurality of second repair fuse units configured to set second fuse information based on the sequentially outputted TSV defect information, and selectively drives the TSVs in response to the second fuse information.
2. The semiconductor system of claim 1 , wherein at least one of the semiconductor chips further comprises:
a plurality of first latch units, each allocated to the respective TSVs, configured to store the first fuse information set in the plurality of first repair fuse units.
3. The semiconductor system of claim 2 , wherein the plurality of first latch units are composed of a shift register which is controlled by a clock signal.
4. The semiconductor system of claim 2 , wherein at least one of the semiconductor chips further comprises:
a common TSV selection unit configured to sequentially receive the first fuse information outputted from the first latch units, and to selectively drive the TSVs.
5. The semiconductor system of claim 2 , wherein the TSVs comprise a plurality of normal TSVs and a plurality of redundant TSVs, which make a pair.
6. The semiconductor system of claim 5 , wherein at least one of the semiconductor chips further comprises:
a plurality of first TSV selection units, each allocated to a pair of the normal and redundant TSVs, configured to receive the first fuse information outputted from the first latch units and to selectively drive the normal TSVs and the redundant TSVs.
7. The semiconductor system of claim 5 , wherein the controller further comprises:
a plurality of second TSV selection units, each allocated to a pair of the normal and redundant TSVs, configured to selectively drive the normal TSVs and the redundant TSVs in response to the second fuse information set in the plurality of second repair fuse units.
8. The semiconductor system of claim 1 , wherein the controller further comprises:
a plurality of second latch units, each allocated to the respective TSVs, configured to store the sequentially outputted TSV defect information.
9. The semiconductor system of claim 8 , wherein the plurality of second latch units are composed of a shift register which is controlled by a clock signal.
10. The semiconductor system of claim 8 , wherein the controller further comprises:
a repair information storage unit configured to store the sequentially outputted TSV defect information, and simultaneously transfer the stored TSV defect information to the second latch units in response to a clock signal.
11. The semiconductor system of claim 1 , further comprising:
a defect information transfer TSV configured to transfer the sequentially outputted TSV defect information from at least one of the semiconductor chips to the controller.
12. The semiconductor system of claim 11 , wherein the defect information transfer TSV includes a plurality of TSVs which are connected through a plurality of connection lines in parallel.
13. A semiconductor system comprising:
a controller;
a semiconductor device comprising a plurality of stacked semiconductor chips stacked over the controller, and a plurality of through-silicon vias (TSVs) configured to commonly transfer a signal to the plurality of stacked semiconductor chips; and
a defect information transfer TSV configured to transfer TSV defect information sequentially outputted from at least one of the semiconductor chips to the controller,
wherein the controller comprises:
a plurality of first repair fuse units configured to set first fuse information based on the TSV defect information; and
a plurality of first TSV selection units configured to selectively drive the TSVs in response to the first fuse information.
14. The semiconductor system of claim 13 , wherein the controller further comprises:
a plurality of first latch units configured to store the TSV defect information.
15. The semiconductor system of claim 14 , wherein the plurality of first latch units are composed of a shift register which is controlled by a clock signal.
16. The semiconductor system of claim 14 , wherein the controller further comprises:
a repair information storage unit configured to store the TSV defect information sequentially outputted, and simultaneously transfer the stored TSV defect information to the first latch units in response to a clock signal.
17. The semiconductor system of claim 13 , wherein at least one of the semiconductor chips comprises:
a plurality of second repair fuse units configured to set second fuse information corresponding to the TSV defect information; and
a plurality of second latch units configured to store the second fuse information.
18. The semiconductor system of claim 17 , wherein the plurality of second latch units are composed of a shift register which is controlled by a clock signal.
19. The semiconductor system of claim 17 , wherein at least one of the semiconductor chips further comprises:
a common TSV selection unit configured to sequentially receive the second fuse information outputted from the second latch units, and to selectively drive the TSVs.
20. The semiconductor system of claim 17 , wherein the TSVs comprise a plurality of normal TSVs and a plurality of redundant TSVs, which make a pair.
21. The semiconductor system of claim 20 , wherein at least one of the semiconductor chips further comprises:
a plurality of second TSV selection units, each allocated to a pair of the normal and redundant TSVs, configured to receive the second fuse information outputted from the second latch units and to selectively drive the normal TSVs and the redundant TSVs.