Semiconductor memory device
According to one embodiment, a semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The memory cells are stacked above a semiconductor substrate, and each includes a charge accumulation layer and control gate. The word lines are coupled to the control gates. The driver circuit repeats a programming operation to write data in a memory cell coupled to a selected word line. In the programming operation, a first voltage is applied to the selected word line, a second voltage to a first unselected word line, and a third voltage to a second unselected word line. The control circuit steps up the first voltage and steps down the second voltage in repeating the programming.
1. A semiconductor memory device comprising:
a plurality of memory cells including current paths coupled in series, and each including a charge accumulation layer and a control gate, the plurality of memory cells being stacked above a semiconductor substrate;
a plurality of word lines coupled to the control gates;
a driver circuit configured to repeat a programming operation to write data in a memory cell coupled to a selected word line, wherein a first voltage is applied to the selected word line, a second voltage is applied to a first unselected word line, and a third voltage is applied to a second unselected word line, in the programming operation; and
a control circuit configured to step up the first voltage and step down the second voltage in repeating the programming operation;
wherein the first unselected word line is adjacent to the selected word line.
2. The device according to claim 1 , wherein the control circuit steps down the second voltage after the number of times of repetition of the programming operation has reached a first count.
3. The device according to claim 1 , wherein the control circuit holds the second voltage constant after the number of times of repetition of the programming operation has reached a second count.
4. The device according to claim 1 , wherein
the memory cell is configured to hold data having not less than four levels in accordance with a threshold voltage, and
the second voltage is stepped down when writing a level having a highest threshold voltage among the not less than four levels.
5. The device according to claim 1 , wherein the control circuit steps down the second voltage after the first voltage has reached a first threshold value.
6. The device according to claim 1 , wherein the control circuit holds the second voltage constant after the first voltage has reached a second threshold value.
7. The device according to claim 1 , wherein the control circuit holds the third voltage constant in repeating the programming operation.
8. The device according to claim 1 , wherein the control circuit steps up the third voltage in repeating the programming operation.
9. The device according to claim 1 , wherein
the second voltage and the third voltage turn on the memory cell, and
the first voltage is higher than the second voltage and the third voltage.
10. A data write method of a semiconductor memory device including a plurality of memory cells including current paths coupled in series, and stacked above a semiconductor substrate, comprising:
programming data in a selected memory cell by applying a first voltage to a gate of the selected memory cell, a second voltage to a gate of a first unselected memory cell, and a third voltage to a gate of a second unselected memory cell; and
repeating the programming while stepping up the first voltage and stepping down the second voltage;
wherein the first unselected memory cell is adjacent to the selected memory cell.
11. The method according to claim 10 , wherein the second voltage is stepped down after the number of times of repetition of the programming has reached a first count.
12. The method according to claim 10 , wherein the second voltage is held constant after the number of times of repetition of the programming has reached a second count.
13. The method according to claim 10 , wherein
the memory cell is configured to hold data having not less than four levels in accordance with a threshold voltage, and
the second voltage is stepped down when writing a level having a highest threshold voltage among the not less than four levels.
14. The method according to claim 10 , wherein the second voltage is stepped down after the first voltage has reached a first threshold value.
15. The method according to claim 10 , wherein the second voltage is held constant after the first voltage has reached a second threshold value.
16. The method according to claim 10 , wherein the third voltage is held constant in repeating the programming.
17. The method according to claim 10 , wherein the third voltage is stepped up whenever the programming is repeated.
18. The method according to claim 10 , wherein
the second voltage and the third voltage turn on the memory cell, and
the first voltage is higher than the second voltage and the third voltage.