Erase techniques and circuits therefor for non-volatile memory devices

1. A method comprising:

applying a first voltage to a memory cell;

applying again the first voltage to the memory cell when the memory cell have not been shifted to an erased condition;

applying a second voltage to the memory cell when the memory cell have not still been shifted to an erased condition, the second voltage being higher than the first voltage;

applying a third voltage to the memory cell when the memory cell is not in the erased condition after applying the second voltage, the third voltage being higher than the second voltage;

applying the second voltage at least one more time prior to applying the third voltage;

wherein the first voltage is applied a first number of times and the second voltage is applied a second number of times, each of the first number and the second number is plural and the first number is equal to the second number; and

wherein the first number is set according to the following equation:

N train=( T max× V step)/{( V max− V min)× T pulse}

wherein Ntrain is the first number, Vmax is a maximum voltage permitted to be used in an erase operation, Vmin is a minimum voltage to be used in the erase operation, Tmax is a maximum time allowed for the total erase operation, Vstep is an amount of voltage difference between the first voltage and the second voltage, and Tpulse is the time duration of the erase operation.

2. The method of claim 1 comprising:

identifying a gap between a minimum voltage and a maximum voltage, the minimum voltage being used in an erase operation to have an erase effect on a memory cell block, the maximum voltage being used in an erase operation to prevent an undesired effect, and

applying the method of claim 1 when the gap is less than a defined amount.

3. The method of claim 1 , further comprising:

applying the first voltage to the memory cell at least one more time prior to applying the second voltage.

4. The method of claim 1 , further comprising:

applying the second voltage to the memory cell at least one more time when the memory cell is not in the erased condition.

5. The method of claim 1 , further comprising:

applying the third voltage to the memory cell at least one more time when the memory cell is not in the erased condition.

6. The method of claim 1 , wherein the memory cell is structured in a NAND type.

7. The method of claim 1 , wherein each of the first and second voltages is supplied to a well of the memory cell.

8. A method comprising:

applying a first voltage to a memory cell;

applying again the first voltage to the memory cell when the memory cell have not been shifted to an erased condition;

applying a second voltage to the memory cell when the memory cell have not still been shifted to an erased condition, the second voltage being higher than the first voltage;

applying a third voltage to the memory cell when the memory cell is not in the erased condition after applying the second voltage, the third voltage being higher than the second voltage;

applying the second voltage at least one more time prior to applying the third voltage;

wherein the first voltage is applied a first number of times and the second voltage is applied a second number of times, each of the first number and the second number is plural and the first number is equal to the second number; and

wherein memory characteristics conform to the following condition

( T max× V step)/( V max− V min)> T erase_min

Tmax being a maximum time allowed for total erase operations, Vstep being an amount of voltage difference between the first voltage and the second voltage, Vmax being a maximum voltage permitted to be used in an erase operation, Vmin being a minimum voltage to be used in the erase operation, and Terase_min being a minimum time necessary to successfully erase the memory cell.

9. The method of claim 8 , further comprising:

applying the first voltage to the memory cell at least one more time prior to applying the second voltage.

10. The method of claim 8 , further comprising:

applying the second voltage to the memory cell at least one more time when the memory cell is not in the erased condition.

11. The method of claim 8 , further comprising:

applying the third voltage to the memory cell at least one more time when the memory cell is not in the erased condition.

12. The method of claim 8 , wherein the memory cell is structured in a NAND type.

13. The method of claim 8 , wherein each of the first and second voltages is supplied to a well of the memory cell.

14. A method comprising:

inputting data into a memory device so that the memory device performs a memory erase operation on a memory cell included therein;

the inputting comprising:

defining a maximum voltage permitted to be used in the erase operation, the maximum voltage being Vmax;

defining a minimum voltage permitted to be used in the erase operation, the minimum voltage being Vmin;

defining an amount of an erase voltage step used in the erase operation, the amount being Vstep;

defining a maximum time permitted to be used in the erase operation, the maximum time being Tmax; and

varying a first number of pulses used in the erase operation that are a same voltage as each other and a timing duration of each pulse, according to the following equation:

N train=( T max× V step)/{( V max− V min)× T pulse}

wherein the first number is Ntrain and the timing duration is Tpulse.

15. The method of claim 14 , wherein memory characteristics conform to the following condition

( T max× V step)/( V max− V min)> T erase_min,

wherein Terase_min is a minimum time necessary to successfully erase the memory cell.

16. The method of claim 14 , wherein the inputting comprising:

deciding the first number and the timing duration of each pulse.

17. The method of claim 16 , further comprising:

performing, in response to an erase command, the erase operation on the memory cell of the memory device based on the first number and the timing duration of each pulse that have been decided.

18. The method of claim 14 , wherein the memory cell is structured in a NAND type.