Configurable source based/requestor based error detection and correction for soft errors in multi-level cache memory to minimize CPU interrupt service routines

1. A memory system comprising:

a plurality of data sources;

a memory for storing data;

a parity enable data register having a bit corresponding to each of said plurality of data sources; and

a parity generator connected to said parity enable register and receiving data from said plurality of data sources, said parity generator operable to form a set of parity bits corresponding to data from said plurality of data sources and store said data and corresponding parity bits in said memory if said bit of said parity bit enable register corresponding to said data source has a first digital state and store only said data in said memory if said bit of said parity bit enable register corresponding to said data source has a second digital state opposite to said first digital state.

2. The memory system of claim 1 , further comprising:

an error detection status register having a suspend bit;

wherein said parity generator is operable to

store only said data in said memory if said suspend bit has a third digital state,

form parity bits and store said parity bits and said corresponding data in said memory if said bit of said parity bit enable register corresponding to said data source has said first digital state and said suspend bit has a fourth digital state opposite said third digital state, and

store only said data in said memory if said bit of said parity bit enable register corresponding to said data source has said second digital state and said suspend bit has said third digital state.

3. The memory system of claim 1 , wherein:

said memory includes a first memory bank and a second memory bank;

said plurality of data sources includes a first data source of N bits and a second data source having 2N bits;

said parity generator includes a first bank parity generator connected to receive N bits of said first data source, a second parity generator connected to receive N upper half bits of said second data source and a third parity generator connected to receive N lower half bits of said second data source;

a first multiplexer having a first input connected to said first parity generator receiving both said N bits and corresponding parity bits, a second input connected to said second parity generator receiving both said N upper half bits and corresponding parity bits and an output;

a second multiplexer having a first input connected to said first parity generator receiving both said N bits and corresponding parity bits, a second input connected to said third parity generator receiving both said N lower half bits and corresponding parity bits and an output;

wherein the memory system controls said first and second multiplexers to perform one of

select said first input as output of said first multiplexer and select no input as output of said second multiplexer thereby storing said N bits and said corresponding parity bits of said first data source in said first memory bank,

select no input as output of said first multiplexer and select said first input of said second multiplexer thereby storing said N bits of said first data source and said corresponding parity bits in said second memory bank, and

select said second input of said first multiplexer and select said second input of said second multiplexer thereby storing said N upper half bits of said second data source and said corresponding parity bits in said first memory bank and storing said N lower half bits of said second data source and said corresponding parity bits in said second memory bank.

4. The memory system of claim 1 , further comprising:

a third data source having 2N bits;

said parity generator further including a fourth parity generator connected to receive N upper half of bits of said third data source and a fifth parity generator connected to receive N lower half of bits of said third data source;

said first multiplexer further having a third input connected to said fourth parity generator receiving both said N upper half bits and corresponding parity bits;

said second multiplexer further having a third input connected to said fifth parity generator receiving both said N lower half bits and corresponding parity bits;

wherein the memory system further controls said first and second multiplexers to

select said third input of said first multiplexer and select said third input of said second multiplexer thereby storing said N upper half bits of said third data source and said corresponding parity bits in said first memory bank and storing said N lower half bits of said third data source and said corresponding parity bits in said second memory bank.