IP Library Granted Patent US 8,729,600
Granted Patent B2
US 8,729,600 · App. 13/534,530 · Granted May 20, 2014

Insulated gate bipolar transistor (IGBT) with hole stopper layer

Inventors: Yukio Tsuzuki (Nukata-gun, JP); Kenji Kouno (Gifu, JP); Hiromitsu Tanabe (Nukata-gun, JP)
Assignee: DENSO CORPORATION
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Quick Facts
Patent No.
US 8,729,600
App. No.
13/534,530
Granted
May 20, 2014
Kind
B2
Abstract

A semiconductor device has a first conductivity-type semiconductor substrate, second conductivity-type channel regions, and second conductivity-type thinning-out regions. The channel regions and the thinning-out regions are formed adjacent to a substrate surface of the semiconductor substrate. Further, a hole stopper layer is formed in each of the thinning-out regions to divide the thinning-out region into a first part adjacent to the substrate surface and a second part adjacent to a bottom of the thinning-out region. The hole stopper layer has an area density of equal to or less than 4.0×10 12 cm −2 to permit a depletion layer to punch through the hole stopper layer, thereby to restrict breakdown properties from being decreased.

Claims (23)

1. A semiconductor device comprising:

a first conductivity-type semiconductor substrate having a substrate surface;

a plurality of second conductivity-type channel regions disposed adjacent to the substrate surface;

a plurality of second conductivity-type thinning-out regions disposed adjacent to the substrate surface, the thinning-out regions and the channel regions being arranged in a direction parallel to the substrate surface in such a manner that at least one thinning-out region is disposed between the adjacent channel regions;

a first conductivity-type emitter region disposed at a surface layer portion of each of the channel regions;

a first conductivity-type hole stopper layer disposed in each of the thinning-out regions to divide the thinning-out region into a first part adjacent to the substrate surface and a second part adjacent to a bottom of the thinning-out region;

an emitter electrode connected to the emitter region and the first part;

a collector layer disposed in the semiconductor substrate at a position separated from the channel regions and the thinning-out regions; and

a collector electrode electrically connected to the collector layer, wherein

the hole stopper layer has an area density of equal to or less than 4.0×10 12 cm −2 .

2. The semiconductor device according to claim 1 , wherein the first part has an area density of equal to or greater than 1.1×10 12 cm −2 .

3. The semiconductor device according to claim 1 , wherein

the collector layer provides a first conductivity-type cathode layer at a part, and

the semiconductor substrate includes an IGBT section serving as an IGBT element and a diode section serving as a diode element with respect to a direction parallel to the substrate surface, the IGBT section being defined by a section including the collector layer other than the cathode layer, the diode section being defined by a section including the cathode layer.

4. The semiconductor device according to claim 3 , wherein the area density of the first part is equal to or less than 3.5×10 12 cm −2 .

5. The semiconductor device according to claim 3 , wherein the hole stopper layer is disposed also in the diode section.

6. The semiconductor device according to claim 3 wherein

the semiconductor substrate includes a drift region serving as a drift layer, and

the drift region is formed with a lifetime killer.

7. The semiconductor device according to claim 1 , wherein

the semiconductor substrate has a second conductivity-type base layer adjacent to the substrate surface, and a plurality of trenches passing through the base layer to divide the base layer into multiple regions,

the channel regions and the thinning-out regions are provided by the multiple regions of the base layer divided by the trenches, and

each of the trenches is filled with a gate insulation film and a gate electrode, the gate insulation film being disposed on a wall surface of the trench, and the gate electrode being disposed on the gate insulation film.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 27, 2012
From: TSUZUKI, YUKIO; KOUNO, KENJI; TANABE, HIROMITSU
To: DENSO CORPORATION
Reel/Frame 028453/0032 →
Priority Claims (2)
JP 2011-148138 · Jul 4, 2011 · national
JP 2012-094769 · Apr 18, 2012 · national
Continuity (1)
Related Publication 20130009205A1 · Jan 10, 2013