Stereoscopic image display device and driving method thereof

1. A stereoscopic image display device comprising:

a display panel comprising thin film transistors (TFTs) formed at crossings of data lines and gate lines and mxn (m and n are positive integers) number of pixels divided into main subpixels and auxiliary subpixels;

a data driving circuit supplying a data voltage of a two dimensional (2D) image to the data lines in a 2D mode and supplying a data voltage of a three-dimensional (3D) image to the data lines in a 3D mode; and

a gate driving circuit simultaneously supplying gate pulses for selecting the main subpixels and the auxiliary subpixels to a pair of gate lines including neighboring gate lines in the 2D mode and simultaneously supplying gate pulses for selecting the auxiliary subpixels to even-numbered gate lines in the 3D mode, wherein a size of the main subpixels is greater than a size of the auxiliary subpixels.

2. The device of claim 1 , wherein the gate lines comprises:

odd-numbered gate lines for selecting the main subpixels; and

even-numbered gate lines for selecting the auxiliary subpixels.

3. The device of claim 2 , wherein, in the 2D mode, the gate driving circuit shifts gate pulses supplied to the gate lines in units of the one pair of gate lines, and in the 3D mode, the gate driving circuit shifts gate pulses supplied to odd-numbered gate lines and then simultaneously supplies the gates pulse to the even-numbered gate lines.

4. The device of claim 1 , further comprising:

a timing controller configured to supply digital video data of a 2D image and digital video data of a 3D image to the data driving circuit and control an operation timing of the data driving circuit and the gate driving circuit; and

a system board configured to supply the digital video data to the timing controller and supply a mode signal for discriminating the 2D mode and the 3D mode to the timing controller and the gate driving circuit.

5. The device of claim 4 , wherein the gate driving circuit comprises:

a shift register configured to shifting a gate start pulse (GSP) according to a gate shift clock (GSC);

a level shifter configured to adjust a swing width of an output voltage of the shift register to output the same to the gate lines; and

a multiplexer array disposed between output terminals of the shift register and input terminals of the level shifter to select a branch path of an output signal of the shift register according to the mode signal.

6. The device of claim 5 , wherein, in the 2D mode, the multiplexer array simultaneously supplies the output signal from the shift register to the neighboring input terminals of the level shifter, and in the 3D mode, the multiplexer array simultaneously supplies the last output signal from the shift register to even-numbered input terminals of the shift register.

7. The device of claim 1 , wherein, in the 2D mode, the data driving circuit outputs the data voltage of the 2D image in synchronization with the gate pulses simultaneously supplied to the pair of gate lines, and in the 3D mode, the data driving circuit outputs the data voltage of the 3D image in synchronization with the gate pulses supplied to the odd-numbered gate lines and then outputs a black data voltage in synchronization with the gate pulses simultaneously supplied to the even-numbered gate lines.

8. A method for driving a stereoscopic image display device including a display panel comprising thin film transistors (TFTs) formed at crossings of data lines and gate lines and mxn (m and n are positive integers) number of pixels divided into main subpixels and auxiliary subpixels, the method comprising:

supplying a data voltage of a two-dimensional (2D) image to the data lines in a 2D mode;

simultaneously supplying gate pulses for selecting the main subpixels and the auxiliary subpixels to a pair of gate lines including neighboring gate lines in the 2D mode;

supplying a data voltage of a 3D image to the data lines in a three-dimensional (3D) mode; and

simultaneously supplying gate pulses for selecting the auxiliary subpixels to even-numbered data lines in the 3D mode, wherein a size of the main subpixels is greater than a size of the auxiliary subpixels.

9. The method of claim 8 , wherein, in simultaneously supplying the gate pulses to the pair of gate lines including neighboring gate lines in the 2D mode, the gate pulses supplied to the gate lines are shifted in units of the pair of gate lines.

10. The method of claim 9 , wherein, in simultaneously supplying gate pulses to the even-numbered gate lines in the 3D mode, the gate pulses supplied to odd-numbered gate lines are shifted and then the gate pulses are simultaneously supplied to the even-numbered gate lines.

11. The method of claim 8 , wherein, in supplying the data voltage of the 2D image to the data lines in the 2D mode, the data voltage of the 2D image is supplied to the data lines in synchronization with the gate pulses simultaneously supplied to the pair of gate lines.

12. The method of claim 11 , wherein the supplying of the data voltage of the 3D image to the data lines in the 3D mode comprises:

supplying the data voltage of the 3D image to the data lines in synchronization with the gate pulses supplied to the odd-numbered gate lines; and

supplying a black data voltage to the data lines in synchronization with the gate pulses simultaneously supplied to the even-numbered gate lines.