3D non-volatile memory device and method for operating and fabricating the same
A 3D non-volatile memory device includes a plate-type lower select line formed over a substrate, a lower select transistor formed in the lower select line, a plurality of memory cells stacked over the lower select transistor, an upper select transistor formed over the memory cells, and a line-type common source line formed over the substrate and spaced from the lower select line.
1. A 3D non-volatile memory device comprising:
a plate-type lower select line formed over a substrate;
a lower select transistor formed in the lower select line;
a plurality of memory cells stacked over the lower select transistor;
an upper select transistor formed over the memory cells;
a device isolation layer formed in the substrate;
a line-type common source line formed to be contacted with the device isolation layer and horizontally spaced from the lower select line; and
a line-type contact plug formed in parallel with the line-type common source line and formed over the lower select line.
2. The 3D non-volatile memory device of claim 1 , further comprising a well area formed in the substrate between the lower select transistor and the common source line, wherein the common source line is formed over the device isolation layer and the well area.
3. The 3D non-volatile memory device of claim 2 , wherein a channel of the lower select transistor and the common source line have a first conductive type, and the well area has a second conductive type different from the first conductive type.
4. The 3D non-volatile memory device of claim 1 , wherein the common source line comprises a metallic layer.
5. The 3D non-volatile memory device of claim 1 , wherein the lower select transistor comprises:
a channel arranged to project from the substrate and pass through the lower select line; and
a gate dielectric layer interposed between the channel and the lower select line.