Noise shaped interpolator and decimator apparatus and method
Improved interpolator and decimator apparatus and methods, including the addition of an elastic storage element in the signal path. In one exemplary embodiment, the elastic element comprises a FIFO which advantageously allows short term variation in sample clocks to be absorbed, and also provides a feedback mechanism for controlling a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.
1. A decimator apparatus useful in a communications circuit, comprising:
a filter;
a delta-sigma modulator operatively coupled to the filter;
an elastic storage element operatively coupled to the delta-sigma modulator, the elastic storage element having at least one data input port configured to receive data using a first clock signal and at least one output configured to transmit data using a second clock signal substantially independent of the first clock signal, wherein the elastic storage element is configured to supply feedback based on the first clock signal; and
a modulo counter interposed electrically between the modulator and the elastic storage element, wherein the modulo counter is connected between the delta-sigma modulator and a control input of the elastic storage element.
2. The decimator apparatus of claim 1 , wherein the first clock signal is faster than the second clock signal.
3. The decimator apparatus of claim 1 , wherein the elastic storage element comprises a multi-port random access memory (RAM) first-in, first out (FIFO).
4. The decimator apparatus of claim 1 , wherein the elastic storage element comprises at least one data input port configured to receive N samples of input data for each cycle of the first clock signal.
5. The decimator apparatus of claim 1 , wherein the decimator apparatus is configured to absorb variations in a ratio of the first clock signal and the second clock signal.
6. The decimator apparatus of claim 1 , wherein the apparatus forms a frequency-locked loop (FLL).
7. The decimator apparatus of claim 1 , wherein at least the elastic storage element is configured to use Gray coding.
8. A decimator apparatus, comprising:
a filter;
a delta-sigma modulator operatively coupled to the filter;
an elastic storage element having at least one data input port configured to receive data using a first clock signal and at least one output configured to transmit data using a second clock signal substantially independent of the first clock signal; and
a modulo counter connected between the delta-sigma modulator and a write-enable input of the elastic storage element.
9. The decimator apparatus of claim 8 , wherein the first clock signal is faster than the second clock signal.
10. The decimator apparatus of claim 8 , wherein the elastic storage element comprises a multi-port, first-in, first out (FIFO), random access memory (RAM).
11. The decimator apparatus of claim 8 , wherein the elastic storage element is configured to supply feedback based on the first clock signal.
12. The decimator apparatus of claim 8 , wherein the elastic storage element comprises at least one data input port configured to receive N samples of input data for each cycle of the first clock signal.
13. The decimator apparatus of claim 8 , wherein the decimator apparatus is configured to absorb variations in a ratio of the first clock signal and the second clock signal.
14. The decimator apparatus of claim 8 , wherein the apparatus forms a frequency-locked loop (FLL).
15. The decimator apparatus of claim 8 , wherein at least the elastic storage element is configured to use Gray coding.
16. A decimator apparatus, comprising:
a filter;
a delta-sigma modulator operatively coupled to the filter;
an elastic storage element having at least one data input port configured to receive data using a first clock signal and at least one output configured to transmit data using a second clock signal substantially independent of the first clock signal, the elastic storage element including read and write pointers each including a Gray code counter; and
a modulo counter connected between the delta-sigma modulator and a write-enable input of the elastic storage element.
17. The decimator apparatus of claim 16 , wherein the first clock signal is faster than the second clock signal.
18. The decimator apparatus of claim 16 , wherein the elastic storage element is configured to supply feedback based on the first clock signal.